ACM TACO

From @UWMadisonECE, #BitSAD enables simulation and hardware generation of general purpose #bitstream computing circuits (w/ population coding support for parallelization) -@darsnack dl.acm.org/doi/abs/10.114…

An extension of Top-down #Performance_Analysis enables sharp architectural insights as #Moore's_Low slows -- Ahmad Yasin dl.acm.org/doi/abs/10.114…

Processing-in-(Nonvolatile)-Memory #PIM can enable energy-efficient and high-performance Binary Neural Network #BNN accelerators dl.acm.org/doi/abs/10.114…

Researchers at @LehighU design a #framework based on #LLVM #compiler to support #TM in #C++ by forbidding explicit #self-abort, and by introducing an #executor-based mechanism for running transactions.- Pantea Zardoshti dl.acm.org/doi/abs/10.114…

Research @iitmadras #iitm PACE lab #optimizes remote communication (by a large factor) for PGAS based #parallel programming languages using #program analysis and transformation techniques. @KrishnaNandiva @iitmcse @acmtaco: doi.org/10.1145/3345558

@CAL_NTNU researchers show that pre-computing iterative stencil loop coefficients across multiple iterations at design time enables #FPGA-based #accelerators that have 7.7X higher throughput than the current state-of-the-art. dl.acm.org/doi/abs/10.114…

A #hardware-based high-frequency checkpointing mechanism is explored to achieve efficient #inmemory data persistence on #NVM - Song Wu, dl.acm.org/citation.cfm?i…

Machine learned surrogate #performance models speed up iterative polyhedral program #optimization and identify relevant performance aspects. dl.acm.org/citation.cfm?i…

Researchers at @Harvard build #deeplearning models to predict #cpu performance based on public datasets @EmmaWang926: dl.acm.org/citation.cfm?i…

Statistical regression can predict the occurrence of #silentstores with over 85% of accuracy - Fernando Pereira: dl.acm.org/citation.cfm?i…

Research at @HKUniversity makes #GPU better at conditional branching by enabling in-kernel thread-data remapping. dl.acm.org/citation.cfm?i…

Researchers at #NEU demonstrate a highly effective and light-weight technique to exploit data block cooperation that advances error correction capability of #NVM. dl.acm.org/citation.cfm?i…

"#Compiler #optimization can reach the #performance of optimized #BLAS libraries without the need for an external implementation or automatic tuning - Roman Gareev, Tobias Grosser, and Michael Kruse #LLVM" dl.acm.org/citation.cfm?i…

Research @tcd #SCSS #stglab shows #PASM saves 54% ASIC power & 64% FPGA power with only 12% latency increase in CNN MACs @jpgarland @acmtaco dl.acm.org/citation.cfm?i…

With LAPPS, adding few simple lines of code to shared memory-oriented @ChapelLanguage applications makes them scale on #supercomputers #productivity @ekayrakli dl.acm.org/citation.cfm?i…

#Benzene efficiently utilizes distributed SRAM/STT-RAM hybrid #cache to achieve 47% reduction in its energy consumption. - Namhyung Kim, Junwhan Ahn, Kiyoung Choi, Daniel Sanchez, Donghoon Yoo, and Soojung Ryu dl.acm.org/citation.cfm?i…

Adaptive Turbo Boost (ATB): Adaptively using Decoupled Look-Ahead(DLA) as a boosting strategy for improving #performance and #energy efficiency of conventional #turboboost. - Kondguli and Huang. dl.acm.org/citation.cfm?i…

Research at @DrexelUniv VANDAL shows that trace-based models can speed up simulation of future #HPC processors by 18.7x. dl.acm.org/citation.cfm?i…

#HAShCache is the first work to use heterogeneity-aware mechanisms to manage the die stacked DRAM as cache to improve performance of integrated CPU+GPGPU processors over SOTA #HPC #microarchitecture @IIScCSA @adarsh_patil dl.acm.org/citation.cfm?i…

#HAShCache shows that using a die stacked DRAM as cache for integrated heterogeneous CPU+GPGPU processors results in 200% performance improvement in overall system performance @IIScCSA @adarsh_patil #HPC #microarchitecture dl.acm.org/citation.cfm?i…