sigma capitalist

@Aaronwei3n This is not what Nvidia CFO said though, in a follow-up interview after their earnings call: finance.yahoo.com/news/nvidia-cf… Where is your quote from?

Wow, so the $20B is actually only standalone CPUs. _ CPUs Our guide for $20B in revenues is for this year and is for just standalone CPUs, it doesn’t include Grace Blackwell or Vera Rubin modules that include the CPU.  Those sales are separate and excluded from the $20B. We will give more color on how we see the CPU TAM shaping up and where we believe we fit in at Computex in Taiwan in June. Standalone CPU isn’t a new business for us, we had Grace standalone sales since last year.  We wouldn’t categorize it as new business, it’s something that we had shipped into previously, so this isn’t going from $0 to $20B in a year. We recognize that we will be bigger than AMD was in Datacenter CPU in revenues based on our guidance and consensus AMD est. The workloads our CPUs are designed to service are across all that Jensen spoke to – it’s head node, it’s orchestration, it’s tool use, it’s storage, it’s all of the above.  We aren’t targeting one niche AI companion workload with our CPUs. $NVDA

@phithetasigma Do you know how much ENEOS want to own JX? I saw you tweeted about the number 1/3, but I cannot find any evidence. Thx

JX Advanced Metals $5016.T had just released a notice on the pricing for their share buyback (i.e. tender offer price): ¥3,401 per share The conversion price for the shares underlying their convertible bond offer which closed yesterday was: ¥4,860 per share This means JX is effectively buying back shares at a 30% discount to the price of shares they are selling forward through the convertible bond This situation is so bizarre - accentuated by how the stock has been trading - that I have no words to describe Markets are truly broken, sometimes

@jukan05 "Avoid retimer DSPs at all costs"

In the AI Era, the 'Retimer' Rises — The Key Component That Resuscitates Signals The retimer is emerging as a hidden core component of the AI chip era. A retimer is a part that sits between chips, reviving weakened signals and retransmitting them. Its role is growing as communication speeds between the CPU and GPU increase. Inside a server, CPU-to-CPU and CPU-to-GPU communication runs over PCIe (Peripheral Component Interconnect Express). As PCIe advances through each generation, communication speeds rise, giving way to channel loss — the phenomenon in which the signal weakens and its waveform becomes distorted. On the 24th, a senior official at a domestic system semiconductor company said, "CPUs talk to each other, and CPUs and GPUs communicate heavily over PCIe," adding, "As these distances grow longer, speeds get faster, and channel counts increase, chips called 'retimers' have started to see widespread use." Today's high-performance servers use PCIe 5.0, which runs at 32 GT/s (gigatransfers per second). At this speed, even with ultra-low-loss printed circuit boards (PCBs), the distance over which a signal can arrive intact is extremely short. The retimer revives the dying signal at this point, enabling high-speed processor-to-processor communication even over longer distances. In the past, redrivers were used. A redriver only amplifies a weakened signal and cannot fully restore it. The retimer, by contrast, restores the signal completely. This difference is what is driving up demand for retimers. The key point is that as PCIe advances through each generation, faster speeds shorten the distance a signal can travel intact. As that distance shrinks, more retimers are needed. Demand is bound to grow exponentially. The same official forecast, "As communication speeds rise, the number of retimers required will increase several times over from current levels." Astera Labs, a leading retimer company, is also seeing revenue grow. Its first-quarter revenue this year came in at $308.4 million, nearly double the figure from the same period a year earlier. $ALAB

@grok Who is the largest space debris removal and on-orbit service pure-play provider in the world?

Pop quiz time 🎈 In the spirit of celebrating SpaceX's S-1 filing, this idea drop is about space There are now tens of thousands of satellites in geostationary/low-earth orbits (LEOs), with the same scale order of new ones to be launched in the coming years. This give rise to issues such as on-orbit servicing and space debris One company stands out in this very niche segment - they provide services including monitoring & inspection of satellites and objects, extension of satellites' operational lives, removal of space debris, and decommissioning of end-of-life (EOL) satellites. They are still in heavy R&D / development phase so there is a long runway to profitability I have a brief thesis on this name but let's have some fun with Grok (see comments)

Can't compare ASPs for like but I think the total LPDDR dollar content growth in a rack could outpace HBM given the rising importance of CPUs. There are also emerging accelerator/XPU architectures that bypass HBM altogether. I also believe the production cost/gross margin on a net-yield basis is/will continue to be better than HBM

@phithetasigma Interesting, ASPs vs HBM4?

This may be a contrarian view - but I think SOCAMM2 LPDDR5X is far more significant than the HBM4/4E roadmap Reasons: high-volume production ready, yields and commercial deployment Nvidia is using SOCAMM2 LPDDR5X in Vera Rubin (to be supplied by all three majors - Micron, Hynix and Samsung), with AMD to follow with deployment in EPYC Verano next year 2027. Not sure where Intel is with this To watch: JEDEC standards for SOCAMM2 LPDDR6

For those hypothesizing Qualcomm's sale of ARM-based custom data centre CPU chips to Meta (or anyone for that matter) - Make sure to track the ongoing litigation between Qualcomm and ARM: courtlistener.com/docket/6844779… Round 1 (ARM vs Qualcomm/Nuvia) closed in Sep 2025, in favour of Qualcomm/Nuvia We are in early innings of round 2 (Qualcomm countersuing ARM) It's reasonable to assume that Qualcomm is hedging its options - by recruiting Sailesh Kottapalli (Intel's former Chief Architect for Xeon server processors) - perhaps preparing a pivot to x86 ISA, that explains the exodus of the Nuvia founding team early this year

@LDLoeb @BenBajarin Nvidia CFO's response during the phone interview with Yahoo Finance seems to allude to Grace + Vera chips in both standalone and systems configurations. $20B refers to fiscal 2027, I believe

@BenBajarin @phithetasigma So is the $20 bn stand alone Grace and stand alone Vera for fiscal ‘27? Is it Vera for fiscal ‘27 (effectively 3-6 months)? Some other combination/period?

On Nvidia’s CPU revenue guidance – Most, if not all, the sell-side analysts I know of have assumed the $20B CPU revenue guidance to be 100% from Vera CPU standalone sales (not including Vera CPUs in Vera Rubin systems). Can’t fault them given how this figure was framed I had to replay the Nvidia earnings call to confirm what was said about the CPU revenue number 1 - Excerpts from the prepared remarks by Nvidia CFO (Colette): Building on the success of our Grace CPU, Vera is arriving just in time to meet this inflection. […] Vera CPU opens a brand new $200 billion TAM for NVIDIA, a market we have never addressed before. And every major hyperscale and systems maker is partnering with us to get it deployed. We have visibility to nearly $20 billion in total CPU revenue this year, setting us up to become the world leading CPU supplier. 2 - Excerpts from the Q&A section: Vivek Arya (BofA Securities analyst): […] And then secondly, the $20 billion number that you gave, is that for standalone Vera CPUs, or is that kind of already included in that Vera as part of Vera Rubin? Jensen Huang: The 20 billion is for standalone CPUs. And remember, we have Vera used in 3 ways. As a standalone - 4 ways. Let me just start with the one that you already know The first way is Vera Rubin. And we will sell millions of Rubins and every two of them is connected to a Vera. And, of course, we price those too. And they are properly priced. And so that is the number one use case The second use case is Vera standalone CPU The third is Vera with CX9 and the software stack for storage. And then Vera in CX9 with the software stack for security and compute isolation and confidential computing So, each one of those use cases is built on Vera And my sense is that we will be supply constrained throughout the entire life of Vera Rubin. There are four different use cases of it. But, anyhow, the answer to your question is, the 20 billion is a standalone. Nvidia CFO then went on a phone interview with Yahoo Finance yesterday morning – during which the interviewers zoomed in on the 20 billion number: Q: When you talked about that 20 billion, is it the 20 billion as in the CPUs included with Vera Rubin, and then the standalone units as well, or is it the standalone on its own that is the 20 billion? A: it is actually both. As you have seen, already with Grace Blackwell. Grace with it, we have had standalone. And we will see it along with those full systems as well. And then again, with Vera Rubin, we are going to see more of that as well Here’s the interview link: finance.yahoo.com/news/nvidia-cf… With this new update, it is going to be more challenging than before to project the potential bit demand for LPDDR (versus when assuming the $20B to be from 100% Vera CPU sales) given that we now have not only different sales configurations for Vera, but also the sales split between Grace and Vera CPUs, both of which have different ASPs There are also two Grace CPU variants: Superchip (144 cores) and C1 (72 cores). Grace Superchip carries three LPDDR5X memory module options (240GB/480GB/960GB) whereas C1 has 120GB/240GB/480GB on-module memory options One reasonable assumption is for Vera sales to begin in Q3 this year (as part of Vera Rubin systems) followed by standalone Vera sales ramp in 2027 Given that the $20B figure for this year is quite large, one can also assume that this is anchored by revenue booked from the sales of standalone Grace CPU servers being shipped to Meta

@BenBajarin Yea i think CPU demand/shipments are kinda known. What analysts have been more focused on after their latest earnings is triangulating LPDDR bit demand with the CPU numbers because that could have profound impact on consumer/mobile devices for another few years

@phithetasigma He gave us this lead at GTC in our QA so a few of us could see it coming.

@jukan05 I think they are using 48GB LPDDR5X, not 192GB as claimed by KIS

Rumor: As memory prices have surged, memory has come to account for an excessively high share of the BOM, so Nvidia is reportedly carrying out some system-level optimizations. Internally, the company is said to be discussing reducing the amount of system DDR memory in some Vera Rubin configurations — translator’s note: this likely refers to LPDDR — while keeping HBM capacity unchanged.

Nikkei Asia: Japan reactor makers project record sales in nuclear power resurgence 1st order names: Hitachi $6501.T Mitsubishi Heavy Industries $7011.T IHI $7013.T 2nd order names: Japan Steel Works $5631.T Okano Valve Manufacturing $6492.T TVE $6466.T Hitachi is also developing the next-generation small modular reactor (SMR) with GE Vernova $GEV. Construction of the reactors will be in Tennessee and Alabama, where the Japanese and U.S. governments have agreed to invest up to $40B asia.nikkei.com/business/energ…

Was just looking into how Vera is connected to SOCAMM LPDDR5X. They get up to 1.2TB/s on 8 SOCAMM by 4 LPDDR5X (8 x 4 x 9.6Gb/s/bit x 32-bit package), and they seem to be using 48GB modules, which SOCAMM can support up to 256GB (I think). So bandwidth-wise, LPDDR5X is already on par with HBM3E, but with much higher capacity cap To match HBM4 bandwidth, I think that's where we gotta look at LPDDR6. Say they can support up to 14.4Gb/s/bit pin speed (JEDEC spec), and using the same packaging, they can probably get up to close to 2TB/s? Again, I believe LPDDR6 will have higher density/capacity vs HBM4 Not sure what I'm missing. Shall see what you come up with

Preview of intro and table of contents. HBM is a dumb solution for I/O issue. Correct solution (optics driven by clock-forwarded SerDes) can use LPDDR or DDR.

On Nvidia’s Vera CPU – First, let’s revisit the CPU architecture (see attached image) and its bundled memory The referenced SOCAMM is a data centre class modular form factor for LPDDR5X (not to be conflated as two different things) Now, 1 LPDDR5X DRAM die = 9.6Gbps/bit (max). Assuming a 32-bit package, 1 LPDDR5X DRAM package = 9.6 x 32 = 307.2Gbps (~38GB/s) bandwidth 1 SOCAMM is constructed using four LPDDR5X DRAM packages. Total bandwidth per SOCAMM = 38 x 4 = ~154GB/s The Vera CPU setup uses 8 SOCAMM (8-channel), and therefore has 8 x 154 = ~1.2TB/s of bandwidth The 1.5TB refers to the capacity. Assuming 32 (8 x 4) LPDDR5X DRAM packages in 1 Vera CPU, this infers the use of 48GB DRAM packages (not 192GB), i.e., 32 x 48. This could be for thermal/power management reasons In short, each Vera CPU set up = 8 SOCAMMs = 32 LPDDR5X DRAM packages = 1.5TB capacity (32 x 48GB) = up to 1.2TB/s of bandwidth Second, on market opportunity Nvidia guided visibility into ~$20B of CPU revenue this year. What is unknown is how this breaks down into sales configurations (and by extension, the memory modules/density types that may be required) Possible configurations: 1 – as part of Vera Rubin. Assuming NVL72 setup (72 Rubin GPUs, 36 Vera CPUs), total LPDDR5X memory capacity = ~55TB (36 x 8 x 4 x 48), which could potentially be higher if they use higher-capacity memory packages (with liquid cooling) 2 – dedicated Vera CPU racks. Each rack packs 256 Vera CPUs, and therefore up to ~400TB of LPDDR5X memory (256 x 8 x 4 x 48), which could potentially be higher if they use higher-capacity memory packages (with liquid cooling) 3 – individual Vera CPU servers. On the low end will be single and dual socket servers, with one or two Vera CPUs per tray/node respectively. For this configuration, memory capacity = 1.5TB / 3.0TB (assuming use of 48GB modules, with air cooling). Whereas on the high-end, such as the ones being developed by HPE (Cray Supercomputing GX240), this could go up to 640 Vera CPUs = close to ~1000TB. There is also the HGX Rubin NVL8 configuration, with one or two CPUs wired up (with similar memory capacities as a the single/dual socket servers) In short, it’s challenging to accurately size up the total bit demand for LPDDR5X without knowing the exact sales configurations What may be a better play is memory PHY/controllers IP – Each SOCAMM requires 4 x LPDDR5X PHY and memory controllers. For Vera CPU which uses 8 SOCAMMs, each CPU = 32 LPDDR5X PHYs and memory controllers. All that is needed is the average list/sale price for CPU, divide $20B by this number to derive the implied number of Vera CPUs to be sold, that then allows you to derive the dollar content for memory PHY/controllers

For those looking for a read-through to ARM from Nvidia's guidance for Vera CPU chip sales - Remember that Vera's Olympus core is designed in-house literally from scratch, not a pre-designed core set from ARM like the Neoverse V2 core used by Grace What this means is the royalty rate per chip to be paid to ARM for the architectural licensing (covering ISA/test suites only) is likely to be much lower than that paid for core licensing - possibly half or even less (actual figure is heavily negotiated and likely skewed in favor of Nvidia given its scale) Assuming Vera annual chip sales at $20B, and royalty rate of 0.3-0.5%, that works out to $60-100M in total royalty revenues, not $200-400M that would theoretically accrue from core licensing at a 1-2% royalty rate

Smart move because these $2M in tokens are likely worth $200k a few years from now and he's getting equity upside Why bet on Leopold when you have a genius like Sama?

Nailed it - "Bank Indonesia raised the BI-Rate by 50 basis points to 5.25% on Wednesday, the first such move since 2022. The move was anticipated by only one economist in a Bloomberg News survey. Twenty-five analysts had expected a quarter-point move, while 15 predicted a pause" They don't have many options. Their latest reserves (as of Apr) stood at ~$146B. They have burnt through $10B in reserves YTD for FX intervention. Their reserves can probably provide cover for close to 6 months of import needs and external debt servicing. Foreign capital has been exiting their markets and their tax base continues to narrow On top of this, the Indonesian government had just announced the setup of a state-owned body – Danantara Sumberdaya Indonesia (DSI) – which is 99% owned by Danantara, their sovereign wealth fund controlled by the President, that will the sole off-taker of all locally produced natural resources spanning crude palm oil, coal, iron, steel, etc. Nickel, bauxite, copper, tin may all fall within the targeted commodities What this means is that all coal/minerals/crude palm oil producers in Indonesia can only sell to DSI. Direct exports will no longer be allowed. It’s uncertain how prices will be determined, the impact on margins, and how end-buyers may react to this arrangement. There will be ripple effects on the supply chain especially for Asia To me – Indonesia is becoming uninvestible I know of several Singapore public listed companies (palm oil, coal, agribusiness, property, even banks) have significant exposure to Indonesia, and markets haven’t seemed to price the risk in yet bloomberg.com/news/articles/…

I think 2027 will be a pivotal year for memory stocks for several reasons: 1 - Supply-demand dynamics rebalancing going into 2028, with large new capacity ramps coming online. We are also seeing Samsung, Hynix pulling forward their fab build schedules. They are the best placed to assess market dynamics 2 - Market narratives are currently built on a structural demand super-cycle, and indeed they are, but they discount the fact that when faced with constraints, engineers will explore and develop workaround solutions, typically with 2-3 years lead time 3 - AI models are evolving (from general-purpose LLMs to MoEs to domain-specific models). Deployment modes are shifting (from centralized, cloud to localized on-prem/edge). AI workloads are transitioning, not only from training to inference/agentic workflows but also modality from general models to domain-specific models 4 - Given the confluence of these factors, memory architectures and requirements will evolve I am seeing several AI accelerator/silicon startups working on various system architectures and it's interesting how many of them have designed systems with on-chip memory (SRAMs, conventional DRAMs/GDDRs) such that they don’t need writing out to expensive HBMs, and yet manage comparable performance/latency at a much lower TCO. The key seems to lie in their compiler/software stack and interconnect/networking design IMO, memory stocks trading at single-digit P/Es may seem "cheap", but one question to ask - what are their terminal values?