sergey

@zipcpu I like this idea very very much

Hey Dan, I'm thinking of building a PCB with an FPGA, 2x HDMI connectors and 2x GbE connectors. What do you think?

@CodingAndThings Old projects have their own gravity

Back on to my 6502 project today, I think.

I found soldering and 3D printing to be incredibly therapeutic. It's like an 'analog' vacation before diving back into the timing madness of FPGAs.

Further to the previous video there are also some photos of the custom PCB "Toucan" (CAN-FD over Ethernet with the time diagram analyzer)

I finally finished my dual-channel FDCAN over Ethernet device with real-time "Eye-diagram" builder, error injection and Black-jack. I am going to free a lot of space on my workbench.

Nvidia DLSS 5 OFF / Nvidia DLSS 5 ON

@ico_TC 6nm tapeout will look great on the next startup pitch - no need to mention the RTL was untested.

Would you think that a start up would tape out a design on 6nm containing untested RTL?

@observie In medical we use 2 CAN buses as "Operational System" and "Safety System" they both do quite the same but should check each other.

Why two CAN networks? I get this question a lot, so let me defend the decision and see if you agree. A single CAN network can easily support all 12 motors. To confirm, I profiled a single CAN network running 12 motors, and the results show it can be easily supported: x.com/observie/statu… x.com/observie/statu… But: 1. Assigning a separate CAN network to two legs minimizes branching and parallel stubs, which can introduce signal reflections, noise, or impedance mismatches in a single bus setup. 2. Less branching, wiring, and parallel stubs mean cleaner signals and better PHY, potentially fewer errors/retries. 3. The Jetson has two CAN controllers, so introducing a second network is relatively cheap. 4. Splitting messaging load across two buses reduces contention and leaves headroom for expansions, like sensors and actuators (arms? head?). 5. Software cost is minimal.

New Arria 10 FPGA just arrived. Passive cooling all the way. First time working with Altera since university.

@zipcpu Good point. How is the datagram interpreted in this case? Is the master trying to send a write message before the AW address is accepted? What is len?

@sergeykhbr This is a slave interface bug, enabled by a bug in the AXI3 specification (not implementation), that is then discussed in hindsight in the AXI4 specification.

Here's an AXI3 bug I came across (again). The problem is that the slave has no way to tell the master that it cannot handle write interleaving, and so this is how the designer attempted to "fix" the flaw in the AXI3 specification.

@always_ff_rohan @FPGA_Zealot I have the datasheet with the connector descriptions, so getting a RISC-V core running with UART shouldn't take too long - at least until I lose interest, as a first step.

@sergeykhbr nice, looks like @FPGA_Zealot has a good stream on it too youtube.com/watch?v=9ln6Ze…

I decided to get another FPGA, this time with passive cooling - the previous one was way too loud for a home lab. The new one, a Gidel HawkEye-20G-48, is perfect. Gidel has been great and already shared the pinout with me.

@always_ff_rohan The Inspur FPGA was the first one I bought on eBay. After that, I started exploring other options - and then came across this beast: the Intel FPGA PAC N3000. It's actually insane. But additional interfaces of Gitel is more preferable

@sergeykhbr have you looked at INSPUR YHTK-00188-100? It has active cooling with Arria 10 GX.

@always_ff_rohan It's an Altera/Intel Arria 10 fpga. Should work for my purpose. Gidel warned that no support for SFP 40G ethernet connection.

@sergeykhbr I heard that one works only with Gidel proprietary IPs. Not sure if standard xilinx IP will be compatible with that card.

Hopefully this time I'll have better luck with the FPGA-to-FPGA PCIe bridge - preferably without starting a fire.

@ico_TC yeah, I bought some experience

Holy moly, this Inspure FPGA melted its own connector and my cable! Don't leave it unattended without supervision.

@CodingAndThings @pikuma If you figure out how to solve this, please share the knowledge, bro

Me:

@nikalaikina Если представить в виде импульса __/-\__, то front и back становятся очень даже логичными

Ниспадающий и возрастающий не благодарите