Tom Stack

Smartly collecting, storing and distributing electricity is the Tesla energy division's leverage. We should see significant earnings contribution progress in 2023; @elonmusk, @tesla

The Ellison’s will fix this soon hopefully🕵🏻‍♂️

@elonmusk $10,737,418.24

Correct

FSD 14.2.2.5 local navigation in Orlando is much worse than version 14.2.2.4. Really need 14.3 to ease Supervised corrections like incorrect turns and poor commitment on steering decisions.

Here is another one! 👀 Umbrella VS Door… a tale as old as time 🚨 The other story today is that Elizabeth Warren is trying to block an expansion to 401(k) options that 84% of Americans support. She wants only the wealthy to have access to the best investments. Pure greed!

Tesla will source the raw silicon wafers for Terafab from established global suppliers of polished prime wafers (primarily 300mm diameter), as the Terafab is a semiconductor fabrication plant (fab), not a wafer production facility.9 Terafab (launched as a project on/around March 21, 2026) is Tesla’s (joint with SpaceX and xAI elements) massive new in-house AI chip fab. It targets extreme scale: starting at ~100,000 wafer starts per month (WSPM), scaling toward 1 million WSPM to produce 100–200 billion custom AI chips, memory, and advanced packaging annually for Optimus robots, Full Self-Driving, Dojo, and more. It’s located in/near Austin, Texas, with a ~$20–25 billion investment.5 Key Details on Wafer Sourcing •No specific supplier has been publicly announced yet (project is in very early stages—hiring for construction and process roles is just ramping up). Elon Musk and Tesla have not detailed wafer contracts in announcements, earnings calls, or X posts. •Standard industry practice: All major fabs (TSMC, Samsung, Intel, etc.—Tesla’s current foundry partners) buy blank silicon wafers from a handful of specialized upstream manufacturers. Terafab will do the same. These wafers are the starting substrate that gets processed through lithography, etching, doping, etc. •Likely suppliers (based on global market share and industry norms): ◦Shin-Etsu Chemical (Japan) — World’s largest (~30%+ market share). ◦SUMCO (Japan) — Major player. ◦GlobalWafers (Taiwan, with significant U.S. operations/expansions, including Texas) — Often favored for North American fabs due to logistics and “friendlier” supply chain alignment. ◦Others like SK Siltron (South Korea) or Siltronic (Germany). These companies dominate >90% of the advanced silicon wafer market. With Terafab’s Texas location and Tesla’s vertical integration ethos (similar to SpaceX’s in-house PCB production in Bastrop), expect long-term contracts emphasizing secure, high-volume U.S.-friendly supply—possibly leveraging GlobalWafers’ existing or expanded Texas capacity for shorter lead times and reduced geopolitical risk. Why Not In-House Wafer Production? Tesla/SpaceX are not planning to manufacture raw wafers from polysilicon/ingots themselves. That’s an entirely separate, ultra-capital-intensive industry (crystal growth, slicing, polishing) far upstream from chip fabbing. Musk has emphasized simplifying and scaling the fab process (e.g., dedicated lines for single chip designs, FOUP wafer handling, rapid iteration), not entering wafer substrate production.25 Supply of ultra-pure wafers will be a critical (but solvable) input alongside specialty gases, chemicals, and EUV tools. No bottlenecks have been flagged publicly yet—the main driver for Terafab is bypassing external foundry capacity limits at TSMC/Samsung. Details will likely emerge in coming months as construction and supplier deals progress. This fits Tesla’s broader push for U.S. vertical integration in critical tech, much like their battery and PCB efforts. If more specifics drop from Musk or Tesla (e.g., on X or earnings), it could point to a preferred partner.

But what about the quantity of high quality wafers needed to feed Terafab ? I asked Grok about Terafab ‘s possible supply sources: TBD!

Surely this is AI generated?

Michio Kaku, did you say “3AI/Atlas asteroid is talking with whales in Atlantic and Pacific” ???

@elonmusk Grok 4.20 is not available to Premium (only) members

What are your initial impressions of Grok 4.20? Major upgrades are still landing every week.

System on a Wafer (SoW) is already possible and in production with advanced semiconductor fabs as of 2026, particularly through technologies like TSMC’s InFO-SoW and emerging CoW-SoW approaches. Companies like Cerebras have been shipping wafer-scale AI processors (e.g., their Wafer-Scale Engine series) for several years, using full 300mm wafers as monolithic compute units rather than dicing them into individual chips. These overcome traditional reticle limits by avoiding stitching multiple exposures into one die—instead, the entire wafer becomes the “system.” TSMC has pushed this further for AI hyperscalers: •Their System-on-Wafer (TSMC-SoW) enables large arrays of dies on a full 300mm wafer, offering massive compute density, reduced data center footprint, and orders-of-magnitude better performance-per-watt compared to rack-scale clusters. •Tesla’s Dojo supercomputer uses TSMC’s InFO-SoW in production. •Next-gen variants like CoW-SoW (Chip-on-Wafer System-on-Wafer) allow 3D stacking (e.g., logic + HBM memory) on wafer-scale bases, with volume production targeted for around 2027. •Even more advanced SoW-X (CoWoS-based) aims for wafer-scale systems with compute power equivalent to entire server racks (or more), integrating multiple SoCs, stacked HBM, and optical interconnects, with power in the 17,000W range but superior efficiency. This is feasible in leading-edge fabs (e.g., TSMC’s advanced nodes) because SoW leverages wafer-level integration, advanced packaging (CoWoS, SoIC), and doesn’t require monolithic dies larger than the reticle field—though stitching or full-wafer processing handles the scale. Expected reticle size in current advanced fabs (2025–2026) remains the longstanding industry standard: 6 × 6 inches (152 × 152 mm) for EUV and DUV lithography tools from ASML. This yields an exposure field of about 26 × 33 mm on the wafer (4X demagnification) in standard 0.33 NA EUV systems. •For High-NA EUV (0.55 NA, like ASML’s EXE series, now in early adoption/R&D by Intel, TSMC, Samsung), the field is halved in one direction due to anamorphic optics, reducing printable area per exposure to avoid massive throughput penalties. •Larger reticles (e.g., proposals for 6 × 11–12 inches) have been discussed for better productivity (23–50% throughput gains) and to mitigate High-NA limits, with ASML noting compatibility in current stages without optical changes. However, these are not yet standard or in production—mask writers and infrastructure would need upgrades, and the industry sticks to 6×6 for compatibility. •Some advanced packaging interposers (e.g., TSMC’s CoWoS) now approach ~3–9.5 reticle equivalents in effective area via stitching/multiple exposures, with 9.5X CoWoS planned for 2027 to support 12+ HBM stacks. In short, full “system on a wafer” is real and scaling for AI workloads in top-tier fabs today, but it sidesteps pure monolithic reticle limits through innovative wafer-level design and packaging. Traditional single-die chips are still constrained by the ~26×33 mm field. If you’re asking about a specific fab/node (e.g., TSMC N2, Intel 18A), feel free to clarify!

Ask $Grok : System on a wafer possible with this fab? Expected reticle size with this fab?

Grok says this is the 19th century Persian flag. Is this the flag replaced in 1935 with name change to Iran?

Worth time to watch! Hoping for a positive resurrection. Thanks for sharing🙏

@WR4NYGov @bgurley Interesting!

Making progress through the new @bgurley book. There’s a theme that triggers a longstanding “regret”, that I didn’t follow what obviously fascinated me from roughly age 12. This page triggered that again. I’ve had a very good life and had a solid career as a lawyer. I got into it and was reasonably successful. I don’t really regret the path I followed because I had a good first marriage and have two wonderful kids as a result. Still chasing dreams. But I often think I should have chased the tech dream from the beginning. I let a terrible computer science class in my freshman year turn me away from that path. Sometimes I think I should have skipped college, followed my brother to LA, slept on his couch, and scraped together work writing code.

More like many millions of niches! I would lease my niche🕵️‍♀️

@elonmusk Emulate entire company operations digitally... or automate white-collar software work at scale, productivity boost. Tesla and xAI will also have an edge on unique AI agents before physical Optimus arrives.

Yes indeed!

@DavidMoss @wholemars FSD

Which would you rather own & why?

@its_Lexieroy A

Pam Bondi and the FBI are reportedly constructing significant cases against current members of Congress and federal agencies, based on criminal evidence uncovered by DOGE. Should arrests proceed swiftly, regardless of party affiliation? A. Hell yes B. No

I also asked MS Bing: Based on recent industry updates from TSMC regarding CoWoS (Chip-on-Wafer-on-Substrate) and wafer-level integration technologies for high-performance AI and HPC applications: 1Current Technology (as of 2025–2026): •TSMC’s CoWoS-L packaging supports interposers up to 4,719 mm², approximately 5.5× the standard reticle size (using the 830 mm² photomask baseline for TSMC EUV processes). •This supports multi-chiplet assemblies with 12 HBM stacks on advanced substrates. 2Largest Multi-Chiplet / Wafer-Level SoC: •TSMC’s upcoming SoW-X / 9.5× reticle-sized processors are projected to have an interposer area of 7,885 mm², corresponding to 9.5× the standard reticle size. •The substrate for these behemoths measures roughly 120 mm × 150 mm(~18,000 mm²), exceeding typical package sizes and approaching wafer-scale integration. •These chips enable up to four stacked SoIC dies plus 12 HBM4 stacks, offering extreme computational throughput. 3Definition & Clarification: •Reticle size refers to the area of the photomask used in lithography; TSMC’s standard reticle dimension is ~830 mm². •Multiplying this baseline by 9.5 gives the effective “reticle-equivalent size” for the SoW-X chip: •830
 
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830mm •2 •×9.5≈7,885mm •2 • Final Answer The largest System-on-Chip currently being produced (via TSMC’s wafer-level integration) corresponds to a reticle-equivalent size of approximately 9.5×, or: 7 , 885   mm 2 7,885 mm 2 This represents the cutting-edge of wafer-scale, multi-chiplet SoC design in 2026.

What is the wafer retical size of the largest System on a Chip currently produced by chip fabrication businesses? The largest System on a Chip (SoC) currently in production is the Cerebras Wafer Scale Engine 3 (WSE-3), fabricated by TSMC on its 5nm process node. 17 This AI-focused SoC measures 215 mm × 215 mm for a total die area of 46,225 mm², integrating 4 trillion transistors, 900,000 compute cores, and 44 GB of on-chip SRAM. 5 9 2 It is built as a single monolithic die spanning nearly an entire 300 mm wafer, which requires stitching together multiple exposures to transcend the standard reticle field size limit of 26 mm × 33 mm (approximately 858 mm² per exposure) used in modern lithography scanners. 3 16 20 22 23 For comparison, the next-largest production SoCs, such as NVIDIA’s GH100 GPU, have die sizes around 814 mm²—over 56 times smaller—and fit within a single reticle field. Thanks Grok