Jason Yu

We are excited to share AnvilHDL (accepted at #ASPLOS26), a hardware description language with a type system that prevents a common class of bugs (which we call timing hazards) without sacrificing expressiveness for low-level control. Try it online: anvil.kisp-lab.org

Learn more about AnvilHDL through our documentation docs.anvil.kisp-lab.org and preprint arxiv.org/abs/2503.19447 Kudos to my collaborators on AnvilHDL😆@adi4web @mathur_umang @trevorcarlson @prateekatcs #Hardware #Verilog #FPGA #Research

We are excited to share AnvilHDL (accepted at #ASPLOS26), a hardware description language with a type system that prevents a common class of bugs (which we call timing hazards) without sacrificing expressiveness for low-level control. Try it online: anvil.kisp-lab.org

The ACM CCS 2021 conference program is available: sigsac.org/ccs/CCS2021/co…