Codasip

Codasip Studio is a comprehensive processor IP development toolset. It generates both RTL and software development tools from one processor description and also helps with management of configurable designs. Learn more in our recent blog post. codasip.com/2025/06/08/pro…

Compilers are an important part of our customizable and secure RISC-V processor offering. Ramkumar Ramachandra, one of our compiler experts, was presenting about his work at the recent EuroLLVM Developers' Meeting. See the recording of his talk below 👇 youtube.com/watch?v=2Gs-eA…

#ICYMI Developing memory-safe software with CHERI has never been easier! Read our recent press release on Codasip Prime to learn more. codasip.com/press-release/…

Managing variants of processor IP is a tedious job easily leading to expensive errors. In our latest blog, Jaromir Kucny explains powerful Codasip Studio features helping us and our customers manage highly configurable processor IP 👇 codasip.com/2025/06/08/pro…

Breaking the performance limits while keeping the design and verification effort at minimum. This is what we enable with Bounded Customization. See how we deliver more precise and responsive motor behavior with the brand new Codasip L150 RISC-V core. codasip.com/2025/05/08/bou…

Enabling early software development is very important. At Codasip we realize that and provide number of simulation models with our customizable RISC-V processors. Now including MachineWare's SIM-V. codasip.com/2025/04/22/mac…

#RISCVSummitEurope highlight! Using CMSIS for simplified migration to RISC-V Wed 14 at 10:35, in Louis Armand East (S3) By Keith Graham, Vice President of University and Customer Experience Program, Codasip.

#ICYMI We have launched Codasip Prime for #CHERI featuring a high-performance FPGA system, including the processor and peripherals, and a full software development kit. Learn more: codasip.com/press-release/…

Introducing Codasip L150: a 3-stage, 32-bit RISC-V core designed for real-time embedded applications where area and power efficiency are critical. Beyond the efficient baseline architecture, Bounded Customization enables domain-specific optimization. codasip.com/2025/05/08/bou…

We are excited for RISC-V Summit in Paris next week. If you are going, make sure to attend the automotive panel. 📅 Wednesday May 13 at 17:15 Learn more: codasip.com/events/risc-v-…

Wishing you all a very happy #StarWarsDay!  #MayThe4thBeWithYou

@Codasip launches Codasip Prime, the first #CHERI-enabled RISC-V development platform based on the X730 CPU. Built for secure, memory-safe apps in consumer, auto, and defense sectors. #Cybersecurity #Codasip #SecureSoftware #FPGA #EmbeddedSystems electronicsmedia.info/2025/04/29/cod…

Codasip Studio is now integrated with MachineWare’s SIM-V simulator. Learn more 👇 codasip.com/2025/04/22/mac…

🔔 Press release: Codasip launches complete exploration platform to accelerate CHERI adoption codasip.com/press-release/…

#RISCVSummitEurope highlight! Panel: Accelerating Automotive Innovation with RISC-V: The journey from early adoption to industry wide deployment Wednesday, May 14 at 17:15. Learn more about our participation  codasip.com/events/risc-v-…

The winners of the RISC-V Hackathon online have been revealed! Check out the top solutions and learn more about the customization challenge we presented to the contestants. youtu.be/6HtgXuuyP1s?si…

@navyasreemn @risc_v That's awesome! Thanks for joining the hackathon.

I’m deeply appreciative of @risc_v & @Codasip for their hackathon. Their tools helped me optimize a Transformer encoder on RV32I, adding MUL_S7_8 for s7_8 multiplies, DIV_S7_8 for softmax, & MATVEC_4x8_S7_8 for FFN. Cut cycles from 29,930 to 2,884!

We are excited to announce the latest release of Codasip Studio, packed with features to streamline and enhance the custom processor design journey. One of the feature highlights of this release is the integration with MachineWare’s SIM-V simulator. codasip.com/2025/04/22/mac…

Interested in the latest in cybersecurity and #RISCV? Going to the #RISCVSummitEurope in Paris? We are bringing not one, but 4 different posters on CHERI. Make sure to see them and talk to our amazing security architects on site. riscv-europe.org/summit/2025/

At #ew25 we caught up with the team from ipXchange to explain how we utilize CMSIS for simplified migration to #RISCV. Watch the video below! Codasip L110 vs ARM M7: Who wins?  codasip.com/video/codasip-…