Chip design verification consumes up to 70% of the engineering effort on a project, and a significant chunk of that time goes to one task: reading hundreds of pages of natural language specifications and manually translating them into formal, testable representations. We have been working with @FraunhoferIESE on a better approach. Today we are releasing DRAMBench, an open benchmark that measures how well AI systems can formalize JEDEC memory chip specifications into timed Petri net models. Read more: normalcomputing.com/blog/from-spec…