Robert Primas

I am happy to share that, starting from today, I will be working as a research scientist for Intel Labs. Research topics include (Post-Quantum) Cryptography, Hardware Design, and Side Channels 🙂.

I have recently released a new hardware design of the Ascon cipher (github.com/rprimas/ascon-…). It is written in Verilog, is easy to work with, and comes with a very permissive CC0 license. Have fun 😉.

NIST just announced Ascon as the winner of the #NIST #lightweightcryptography project. Congratulations to the Ascon team!

🚨new version of SCALib (v.0.4.2): 1. New features (Multivariate t-test, new operations for SASCA) 2. Improved performances (for SNR and T-tests). 3. AVX2 instructions support on PyPi. 4. Fine grain control on number of thread used. scalib.readthedocs.io/en/stable/ 👇

At the end of September we will host our Graz Security Week Summer School again! More info and a preliminary list of speakers is available here: securityweek.at/2022

We have an open tenure track position in security and privacy at @tugraz: tugraz.at/fakultaeten/cs…. The position comes with a competitive starting package and is part of an environment with more than 60 researchers in #infsec. Apply till November 30.

#ePrint Secure and Efficient Software Masking on Superscalar Pipelined Processors: B Gigerl, R Primas, S Mangard ia.cr/2021/1110

FDTC 2021: workshop on Fault Diagnosis and Tolerance in Cryptography 2021: Virtual #event, Anywhere on Earth, 16 September 2021 fdtc.deib.polimi.it/FDTC21/index.h…

Congratulations to the finalists of the #NIST #lightweight #cryptography standardization process: ASCON, Elephant, GIFT-COFB, Grain128-AEAD, ISAP, Photon-Beetle, Romulus, Sparkle, TinyJambu, and Xoodyak.

#Job PhD Researcher in Post-Quantum Cryptography: Graz University of Technology, Graz, Austria iacr.org/jobs/item/2531

Here comes a very recent publication from our friends at TU Graz 🇦🇹 led by @StefanMangard in which they use IBEX 🐐to test their ideas. You can find their paper "COCO: Co-Design and Co-Verification of Masked Software Implementations on CPUs" here: eprint.iacr.org/2020/1294.pdf

What’s coco? Co-design and co-verification of course! @tugraz’s @barbaragigerl goes over these two for software implementations on #CPUs and how it analyzes the popular 32-bit #RISCV Ibex core at the #RISCVSummit at 12 p.m. PT today: bddy.me/3oB8VaT

Super happy that our paper "A Fast and Compact RISC-V Accelerator for Ascon and Friends" (ia.cr/2020/1083) got the best student paper award at #cardis2020

#Cybersecurity is one of the biggest challenges for our information #society. @SGS_SA and #turaz announce the opening of Lamarr Security Research, focusing on information security, establishing trust in digital systems and to make the world a safer place. tugraz.at/en/tu-graz/ser…

We're hiring a tenure-track professor in security & privacy @tugraz. If you're interested, or know someone, or you're unsure whether you should apply: DM is open. Application deadline is November 26.

Registration for Virtual #CARDIS2020 is open: cardis2020.its.uni-luebeck.de/registration.h… Registration is also *free*, thanks to the generous support of our sponsors @newaetech @NXP @rambusinc @ThalesDigiSec @Riscure See you on November 18/19 cardis.org

@pulp_platform FYI: We have another recent paper that has a strong focus on the Ibex core: ia.cr/2020/1294 This paper will be presented at the upcoming RISC-V Summit.

We are happy to see that our open source work contributes to research in other domains. This is an application of RI5CY (cv32e40p) in cryptographic computations on low-end embedded devices: 'A Fast and Compact RISC-V Accelerator for Ascon and Friends' eprint.iacr.org/2020/1083.pdf