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@System360Cheese

George Cozma | Editor in Chief of Chips and Cheese All opinions are my own

Beigetreten Haziran 2021
203 Folgt1.4K Follower
Cheese
Cheese@System360Cheese·
Well... it looks like it is the beginning of the end for @Tachyum... They are closing their head office in Slovakia due to unpaid debt... This is after a report that the Czech branch is currently being sued for failure to pay empolyees... e.dennikn.sk/5131152/tachyu…
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Cheese@System360Cheese·
@highyieldYT Like I said in the following post, I am of the opinion that it is likely N4C. Although considering that Nvidia's Rubin is on N3 and that is 2 reticle sized dies, I wouldn't rule out the IO dies being on N3 simply because of their size...
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High Yield
High Yield@highyieldYT·
@System360Cheese But a N3 die this large seems odd. Maybe N4, or what do you think?
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Cheese@System360Cheese·
So I would be surprised if the IO dies are still on N6... I know that the analog scaling on newer nodes isn't great, but there is more than just analog on the IO dies such as SRAM and logic... And any reduction in power that the IO dies need means more power to the CCDs...
High Yield@highyieldYT

Some initial assumptions about @AMD's upcoming Zen 6 Venice server CPU👇

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Cheese@System360Cheese·
@Volta700 Yes tho the power reduction would be found more in the SRAM and Logic portions AFAIU... which are a big part of the IO dies... granted this is AMD Rome but as you can see, there is a ton of Logic and SRAM on the IO die...
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Volta@Volta700·
@System360Cheese So even if analog scaling is low or non existent on newer nodes, those portions still use less power?
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Cheese@System360Cheese·
I am not surprised that AMD is chasing stacked L2 tho I doubt that it is going in Zen 6 or Zen 7 personally...
Kepler@Kepler_L2

👀

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Cheese@System360Cheese·
Ahhh... good ol' Ithaca weather... I honestly do miss it... If I had my druthers I would choice to move back there... Honestly, TCAT was amazing when I was there and you could get just about anywhere that you'd need to go... The one thing is that ITH doesn't have many connections
Celia@CeliaBedelia

In defense of NOT using salt, I have to say that it really does destroy things—from plants to even cars. The roads in Ithaca, NY are salted so excessively in the winter that everyone who lives there knows you have to wash your car DAILY in winter (with an undercarriage cleaning) to prevent the whole bottom of your car from rusting away.

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Cheese@System360Cheese·
@jonmasters Sorry Jon you are wrong... the Earth is very clearly a square on the back of a turtle...
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Jon Masters 🏴‍☠️
Jon Masters 🏴‍☠️@jonmasters·
In case you missed it in school: the Earth is round, not flat, meaning that our 2D maps need to use a projection that distorts the size of certain land masses by as much as 14 times. This can make them appear much larger than they actually are
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Cheese@System360Cheese·
Sigh... I was expecting this to some degree but... this is disappointing... 1:4 FP64:FP32 vector for Rubin... and it looks like the FP64 Matrix is using Ozaki for the "200TF" number...
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Cheese@System360Cheese·
@DicksonPau That does not justify abandoning one of your key markets...
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Dickson Pau@DicksonPau·
@System360Cheese Understand this is unfortunate. But Nvidia will generate $300B+ in data center revenue; the science market is just too small compared to the AI market now.
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Cheese@System360Cheese·
@DicksonPau Which is a problem... That sentence in and of itself is a problem... Nvidia functionally ceding the HPC realm to AMD is not a good thing... I want to see strong competition from both Nvidia and AMD so that we can see better HPC products from both companies...
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Cheese@System360Cheese·
@DicksonPau For Science... When you need high precision, YOU NEED HIGH PRECISION... there are no subsitutes...
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Cheese@System360Cheese·
@InstLatX64 I think there is an error in the Zen 5 SOG, because it can do 4 128b or 256b loads per cycle but only 2 512b loads per cycle IIRC...
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InstLatX64@InstLatX64·
According to #AMD #Venice PMCx0AF, #Zen6 will have 6 integer schedulers. Likely 6 AGU-ALU pairs, similar to #Zen4’s 4 and will catch up with #Intel #LionCove. Since Zen6 seems focused on bandwidth, hopefully the 2 loads/clk limit for VEC registers will finally be gone.
InstLatX64 tweet mediaInstLatX64 tweet mediaInstLatX64 tweet mediaInstLatX64 tweet media
InstLatX64@InstLatX64

#AMD released the first official #Zen6 doc: "Performance Monitor Counters for AMD Family 1Ah Model 50h-57h Processors" 69163 v1.00 docs.amd.com/v/u/en-US/6916… Confirmed features: PMCx003: #FP16 PMCx2C0: #MemoryProfiler PMCx0AF: 6 Integer Scheduler (vs 1 central of #Zen5)

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Cheese@System360Cheese·
@JumboShrimp787 @ChipsandCheese9 I calculated the 5.34mm^2 number with 2 of the 2MB slices so it's a Zen 5c core with 4MB of L3 so the overhead of the extra logic from the 2 seperate slices is there in that 5.34 number...
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Jumbo Shrimp
Jumbo Shrimp@JumboShrimp787·
@ChipsandCheese9 Zen 5 (dense) on N3 has only 2 MB of L3 per core, IIRC. Then, the die size per core makes more sense: Zen 5 dense + 2MB L3 on N3E: 5.34 mm2 Zen 6 dense + 4MB L3 no N2P: 5 mm2 Venice-X is (I am guessing) is more likely to be on 12 full core CCD, and have 96 MB of L3 V-Cache
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Cheese@System360Cheese·
@HotAisle Nothing moves faster than the speed of light (in a vaccum 😛)
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Hot Aisle
Hot Aisle@HotAisle·
@System360Cheese True. Still bugs me that this isn't moving faster (than the speed of light).
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