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@System360Cheese

George Cozma | Editor in Chief of Chips and Cheese All opinions are my own

Katılım Haziran 2021
203 Takip Edilen1.4K Takipçiler
Cheese
Cheese@System360Cheese·
@T_Motes They are and Michael does say that.
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Tyler Motes📟🌳🪓
I distrust any review that is gated to specific tests by the manufacturer. This could be completely valid, or it could be that Nvidia is also filtering out valid tests where Vera does not excel that are relevant to their target market.
Phoronix@phoronix

NVIDIA @nvidia Vera CPU Benchmarks: Olympus Cores Delivering The Best Performance Ever Seen On ARM Exclusive first public benchmarks of NVIDIA's new Vera CPU. phoronix.com/review/nvidia-…

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Cheese
Cheese@System360Cheese·
Even as crazy as I am, I am not buying 8 cups of coffee and I AM probably the heaviest coffee drinker Ian knows by a WIDE margin... Most of the time, I am either brewing at home or I am in the Press room where there is free coffee...
𝐷𝑟. 𝐼𝑎𝑛 𝐶𝑢𝑡𝑟𝑒𝑠𝑠@IanCutress

@cptdankkk $15000 is 3000 coffees. 3000 coffees in 365 days is 8.2 coffees per day. I don't know anyone buying 8 coffees a day. Every day.

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𝐷𝑟. 𝐼𝑎𝑛 𝐶𝑢𝑡𝑟𝑒𝑠𝑠
To echo what Cheese said, if you think glass core substrate is in Clearwater Forest, you have a screw loose/have the vaguest idea of how stuff works in semis. Glass core substrate is a 2030s+ technology. I'm serious. It took 10 years for EMIB to get to the point where it yielded enough for production. GCS is going to take longer, much longer. I've only see one example of a GCS 'package' and that was an early research prototype this year, not even by Intel. Whereas CWF is likely already in mass production pending a launch given previous roadmaps. Stop taking your silicon and investment advice from Internet randos. I'm not saying take it from me either, but do the most basic of research and have some understanding.
meng@meng59739449

Clearwater Forest will use 3D Construction (Foveros Direct 3D + EMIB 2.5D) and Glass Substrate , this is first mass-produced chip with Glass Core in JAN 2026

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Cheese
Cheese@System360Cheese·
@corsix @FelixCLC_ It's really fun explaining that a single DDR5 RDIMM is usually 80 bits because of ECC bits...
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@fclc cmp lea char
@fclc cmp lea char@FelixCLC_·
yet more insane itanium shenanigans has entered the conversation
LaurieWired@lauriewired

“if 64 bit is so good then why don’t we have 65 bit architectures” We kinda do, actually. Just mostly as hardware, not pointers. Intel Itanium’s general purpose registers were 65 bits; the last bit was known as a NaT flag. NaT stood for “not a thing”, which was a really interesting way of handling speculative execution. Basically NaT was a poison flag to say “hey this result might be garbage we’ll deal with it later”. Today we don’t really think about it, modern CPUs basically do all of their speculation in hardware…and throw out incorrect guesses without any user awareness. Itanium was essentially a bet that with enough primitives exposed compilers *might* be able to make better decisions at compile-time (versus say, hardware guessing at runtime). A (very) simplified way of putting it, is that on x86 you’re getting constant micro-stalls that the hardware deals with (…die space penalty), where *hypothetically* Itanium with a perfect compiler had no micro-stalls …but really, really bad macro stalls (NaT recovery is a sloooow software fix). Turns out, it was really difficult to write compilers that kept Itanium’s pipeline fed with anything that looks like a normal OS. But, it’s really interesting to see the general idea of “compiler handles the scheduling” coming up again with Cerebras (and arguably, the whole accelerator space)! We’ll see how it pans out… (Itanium was lovingly referred to as the “Itanic” by many)

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@fclc cmp lea char
@fclc cmp lea char@FelixCLC_·
Happy open source RTL day everyone!!!! @Ainekk0 has partnered with @OpenHWFdn to open source the minion/neighborhood RTL that we're actually using for our next chip! And because we have taste, check out the juicy Apache 2.0 license!!!
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neggles (Andi H)
neggles (Andi H)@neggles·
hey @AMDNetworking / @AMD, whatever happened to publishing the SSDK for the AMD-Pensando cards you keep making so much noise about? Or at least updating the documentation to state that it's not available? Or maybe, i dunno, posting updated drivers? Anything? C'mon, guys.
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NASA Artemis
NASA Artemis@NASAArtemis·
Earthset. The Artemis II crew captured this view of an Earthset on April 6, 2026, as they flew around the Moon. The image is reminiscent of the iconic Earthrise image taken by astronaut Bill Anders 58 years earlier as the Apollo 8 crew flew around the Moon.
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Cheese@System360Cheese·
@opinali I'm more thinking about how we remove mass from Earth which affects Earth's gravity... is it a trivial amount, sure... but we still do it... and that affects space-time... Another example is the ability to redirect asteroids which again, manipulates space-time...
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Osvaldo Pinali Doederlein
@System360Cheese No we don't. If you mean stuff like microscopic time dilation in orbit, that's trivial and not meaningfully different than when I have an XXL burrito for dinner and the gravitational field around my potbelly is a bit stronger and also makes my watch go slower.
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Cheese@System360Cheese·
Uhhh... Steve... We do have the ability to manipulate space-time... and we do it nearly everyday as well... along with having been doing it for nearly 70 years... Tho the Soviets beat us to it by about 4 months and kicked off the Space Race because of it...
GamersNexus@GamersNexus

@LisaSu @POTUS @WhiteHouse @mkratsios47 @davidsacks47 Neat! Will your seat be next to the guy who says that American technology can manipulate space and time? Or next to the guy who called for the bailout of Silicon Valley Bank?

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Cheese@System360Cheese·
Well... it looks like it is the beginning of the end for @Tachyum... They are closing their head office in Slovakia due to unpaid debt... This is after a report that the Czech branch is currently being sued for failure to pay empolyees... e.dennikn.sk/5131152/tachyu…
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Cheese@System360Cheese·
@highyieldYT Like I said in the following post, I am of the opinion that it is likely N4C. Although considering that Nvidia's Rubin is on N3 and that is 2 reticle sized dies, I wouldn't rule out the IO dies being on N3 simply because of their size...
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Cheese@System360Cheese·
So I would be surprised if the IO dies are still on N6... I know that the analog scaling on newer nodes isn't great, but there is more than just analog on the IO dies such as SRAM and logic... And any reduction in power that the IO dies need means more power to the CCDs...
High Yield@highyieldYT

Some initial assumptions about @AMD's upcoming Zen 6 Venice server CPU👇

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Cheese@System360Cheese·
@Volta700 Yes tho the power reduction would be found more in the SRAM and Logic portions AFAIU... which are a big part of the IO dies... granted this is AMD Rome but as you can see, there is a ton of Logic and SRAM on the IO die...
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Volta
Volta@Volta700·
@System360Cheese So even if analog scaling is low or non existent on newer nodes, those portions still use less power?
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Cheese@System360Cheese·
I am not surprised that AMD is chasing stacked L2 tho I doubt that it is going in Zen 6 or Zen 7 personally...
Kepler@Kepler_L2

👀

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