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@System360Cheese

George Cozma | Editor in Chief of Chips and Cheese All opinions are my own

Katılım Haziran 2021
204 Takip Edilen1.5K Takipçiler
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Cheese@System360Cheese·
@IanCutress That... that is LA for you 🤣🤣🤣
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Cheese@System360Cheese·
Ah yes... General Physics 1, General Physics 2, and Thermodynamics... Totally math courses... Might as well chuck in Quantum Mechanics, Plasma Physics, and Particle Physics because fuck it, let's make the Math majors suffer!!!
Code Geek@codek_tv

Math in Europe vs Math in America

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Cheese@System360Cheese·
@highyieldYT @magicsilicon But that isn't what the thumbnail says... it says "SMIC N+3 smaller than Intel?" to which the answer is no...
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Cheese@System360Cheese·
Except they didn't... Intel 3 has a M0 of 30nm which is smaller than what SMIC has... They didn't beat Intel even on that single, quite limited, metric... The interesting question here is why did Intel relax the M0 pitch on 18A... maybe @magicsilicon would be willing to answer?
High Yield@highyieldYT

@ChristopheC1980 @SemiAnalysis_ They beat Intel when it comes to the M0. The rest is explained in the video. Ofc you need ppl to click on it. But it wasn’t a lie.

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Cheese@System360Cheese·
@highyieldYT @magicsilicon What you said was "They [SMIC] beat Intel when it comes to the M0." Which is incorrect... they didn't beat Intel because Intel has a node with a 30nm M0, Intel 3...
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Cheese@System360Cheese·
Today is off just swimmingly... First my internet dies for god knows what reason then I find that one of my cats has an injury on her right side all the while I am getting ready to fly to @AMD's AAI and on the way running into traffic to ONT... Hopefully the flight is smooth...
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Cheese@System360Cheese·
NGL, I am looking forward to @hotchipsorg 2026 so that I can ask Nvidia questions such as "Why split your execution ports when a second thread is active?" and "How is your L3 configured in terms of associativity to get to 164 MB?"
𝐷𝑟. 𝐼𝑎𝑛 𝐶𝑢𝑡𝑟𝑒𝑠𝑠@IanCutress

Max Performance? Max Efficiency? Max instruction cache? Max decode width? Max Frequency? Max Die Area? Max L1 bandwidth? Max memory support? No, just Max. You know, max rated frequency at any load. Like a half-dozen other options (or anyone with access to a few BIOS options...)

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Cheese@System360Cheese·
@Silicon_Fly He had that as his fifth innovation seperate of GAAFET...
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Cheese@System360Cheese·
So I disagree with Intel getting to HVM of GAAFETs first... that was Samsung with the Exynos W1000 and Exynos 2500 which were on Samsung's GAAFET process launched and shipping in products by mid-2024 and mid-2025 respectively... which well predates PTL shipping...
Pushkar Ranade@magicsilicon

Intel has been the first to high volume manufacturing on EVERY major innovation in transistor architecture over the last 20 years: 1. Uniaxial strained silicon 2. Hi-k dielectrics and metal gates 3. FinFETs 4. Gate-all-around FET 5. Backside power delivery 🇺🇸 🇺🇸 🇺🇸

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Cheese@System360Cheese·
@Silicon_Fly Sure but that isn't what Pushkar said... He said that Intel was first to GAAFET not GAAFET + BSPDN...
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Cheese@System360Cheese·
@wmf I know SF4X is fairly popular with AI hardware startups and I suspect that IBM will likely fab next gen Z on a Samsung GAAFET node... but other than that... I don't know of any one using Samsung GAAFET nodes...
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Etched@Etched·
We're coming out of stealth. We've built our first racks after a successful A0 tapeout, $1B+ in customer contracts, and $800m raised. Early customer tests show us achieving SOTA throughput, latency, and power efficiency on inference workloads. Our first racks ship this summer.
Etched tweet media
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Cheese@System360Cheese·
@Airport_FRA @bpol_air_fra Oh no, you misunderstand, I get the EES system is not in your jurisdiction, but the layout and design of FRA is and that is a mess... Immigration and emmigration lines being in the way of traffic, having the exit system of the EES at the terminal level instead of at the gate...
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Frankfurt Airport@Airport_FRA·
@System360Cheese Hello George, we understand that waiting in line can be frustrating. Passport control is handled by the German Federal Police, please reach out to them directly at @bpol_air_fra ℹ️
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Cheese@System360Cheese·
@Airport_FRA y'all need to get your shit together... the EES is broken... the immigration line was 3 hours and emmigration line was an hour and a half... The next time I fly into Europe, I am going to avoid FRA if at all possible... y'all have made the worse system possible👏👏👏
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Cheese@System360Cheese·
@Hex_China They have talked plenty about it and there is a lot of info about Rapidus, but risk production is next year with HVM in 2028... If you want to learn more, watch their keynote for Hot Chips 2025...
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hex.v@Hex_China·
@System360Cheese 日本的这个芯片厂什么时候可以投入生产呢?网上似乎没有任何消息
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Cheese@System360Cheese·
That is factually incorrect... Rapidus in Japan is using IBM's 2nm process for their fab and I wouldn't be surprised if Rapidus also licenses this technology as well. Hell, I wouldn't be at all shocked if other folks licenses this tech from IBM for intergration into their nodes.
THE Grand Poobah@real_poobah

@magicsilicon As I wrote in another post, about the only one who cares about IBM process technology these days is the @nytimes. Must be an East Coast thing, because IBM has been irrelevant in the field for 20+ years.

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Cheese@System360Cheese·
@real_poobah If you don't know who Rapidus is, why they exist, or why they licensed IBM's 2nm node, maybe you should do a bit of reading/watching... it's not hard to find info about Rapidus, I'd start with their Hot Chips 2025 Keynote...
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THE Grand Poobah@real_poobah·
@System360Cheese Rapid-who? 😂 I am sure there are edge cases, but they have zero relevance to the broader ecosystem.
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Cheese@System360Cheese·
@IanCutress Either external IO, a la Ponte Vecchio, or structual silicon were the 2 first thoughts that popped into my head...
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