Andes Technology

Join us at RISC-V Now! for “RISC-V: Spanning Datacenter to Edge” by Oliver Jones, CEO of Aion Silicon. Discover how RISC-V is powering AI innovation across datacenter and edge. April 21 | San Jose (DoubleTree). #RISCV #AionSilicon Register: eventbrite.com/e/risc-v-now-b…

Great insights from @DanielNenni on RISC-V's impact on the semiconductor industry. We’re proud to support this evolution by helping drive real-world adoption through initiatives like RISC-V Now! Read more: semiwiki.com/ip/andes-techn… Reg: eventbrite.com/e/risc-v-now-b… #RISCV #SemiWiki

Wrapping up a great week at embedded world! The Andes Technology team connected with partners and the embedded community, with talks from our team and Dr. Su on a RISC-V roadmap panel. Thanks to TASKING for hosting a great dinner. See you next year! #embeddedworld #RISCV

The RISC-V Now! website has been refreshed. New speakers. New partners. More event details. Also announcing our Silicon Valley Deep Dive Day (April 20, 2026) with focused technical sessions. Learn more: riscv-now.com Register: eventbrite.com/e/risc-v-now-b… #RISCV

Ready to power your next innovation? 💡 Visit Andes at #embeddedworld 2026 for exclusive Booth Talks and live tech demos. Don't miss Dr. Charlie Su discussing the future of #RISCV! 📍 Hall 5, Booth 5-119, Kiosk 6 🇩🇪 See you in Nuremberg!

Konnichiwa, Tokyo! 🇯🇵 Join Andes at RISC-V Day Tokyo 2026 Spring! Don't miss our Chairman & CEO Frankwell Lin’s keynote: Powering the Future of Compute with Andes #RISCV 📅 March 5 | 15:30-16:00 Visit us at Booth #5! Details: riscv.or.jp/en/risc-v-day-…

Andes x 10xEngineers: Unleashing #GenAI on #RISCV! The Baltoro compiler now optimizes LLaMA & DeepSeek for our AX46MPV vector cores. 📖 Full News: tinyurl.com/2cgebtkd 🔥 Want to see RISC-V in action? Join our Global Tour: RISC-V Now! by Andes riscv-now.com

@eetimes discusses RISC-V's crossing from academia to commercial reality. RISC-V Now! is this year's dedicated conference for practical insights, tech depth & real deployments. Article: eetimes.com/risc-v-pivots-… RVN!: riscv-now.com Reg: eventbrite.com/.../risc-v-now…... #RISCV

@designreuse explores how #RISCV & #AI are powering low-latency, efficient edge computing for automotive & healthcare apps. With open ISA, RISC-V enables AI/ML customization @ scale. See it in action @ RISC-V Now! Read: design-reuse.com/blog/56242-ris… RVN! Reg: eventbrite.com/e/risc-v-now-b…

We are proud to announce that AndesCore™ N45 and N25F RISC-V processors are now at the core of Phison’s groundbreaking aiDAPTIV+ solution! Phison and Andes continue to lead the way in high-performance, cost-effective AI computing🚀 Learn More: pse.is/8nnrnl

We’re excited to launch RISC-V Now! by Andes - a global conference series focused on deploying RISC-V in production at scale. Taking place in Silicon Valley on Apr 20–21, 2026. Plus events in Hsinchu, Shanghai & Beijing. Learn more: andestech.com/en/2026/02/04/… #RISCV

The RISC-V Annual Report highlights an important shift & not just in adoption, but in architectural maturity. Milestones like RVA23 signal growing alignment on software-ready, scalable RISC-V platforms. As #RISCV evolves, clarity, long-term stability & innovation matter.

This week, the Andes NA sales, marketing, & FAE teams met for an offsite to reflect on 2025 & align on what’s ahead. Joined by colleagues from Taiwan, we strategized, connected, & collaborated at the conference room & pickleball court. Looking forward to 2026!

LTSCT and Andes Technology sign a Strategic IP License Master Agreement to accelerate RISC-V–based advanced semiconductor solutions 🚀 The collaboration enables faster development, scalable IP customization, and long-term innovation for global markets. 🔗tinyurl.com/2c45qb54

As the holidays approach, we want to thank our customers, partners, and the global RISC-V community for your trust and collaboration throughout 2025. Wishing you a joyful and peaceful Christmas from all of us at Andes Technology.

Marc Evans shares a grounded view on what 2025 says about RISC-V: this isn’t a slowdown - it’s maturation. As the ecosystem moves from hype to execution, long-term value comes from the ability to ship, support, and scale. #RISCV Read more: linkedin.com/pulse/enough-h…

📣 New RISC-V co-emulation solution! S2C, MachineWare & Andes deliver a hybrid virtual + FPGA platform for faster, safer chip development—enabling parallel HW/SW verification and shift-left validation. 🔗tinyurl.com/22hygyr3

Last call to register for AI Everywhere by EE Times! Our updated session time is Dec 10, 1:35–1:55 PM EST. Join Simon Wang for “The Third Processor Revolution: AI + RISC-V” to learn why RISC-V’s flexibility & efficiency make it ideal for next-gen AI. Reg: aieverywhere.eetimes.com/?utm_source=an…

Andes AX46MPV Hits Tape-Out! Our 3rd-gen RISC-V vector core for cloud AI is now tape-out at TSMC! The future of cloud AI is here — and AX46MPV is leading the charge. 🔗 Read more: tinyurl.com/28nfxr6k

Andes is honored to be recognized at the 2025 EE Awards with three distinctions, including Best AI Solution Platform and Best IP/Processor. Our deepest gratitude to our partners, customers, and ecosystem for your support as we continue advancing RISC-V and AI innovation. #EETimes