Compute Express Link

Next week, #CXLConsortium will be at Xcelerated Compute in New York City (March 23–24). Visit Stand 18 to learn how #CXL technology is advancing #AI and #HPC. Don’t miss our CXL special presentation on March 24 at 3:00 PM ET. Register with code CXL20: bit.ly/46pqcvV

#CXLConsortium member @Samsung will present a webinar covering overcoming #CXL limitations. Register for the webinar to learn how S-CHMU, CXL-PNM & Pangaea tackle latency, AI bandwidth & virtualization challenges: bit.ly/4uB8r7i

The new paper from @Intel, “The Advantages of Managing the CXL Memory Tier in Hardware,” explores Intel Flat Memory Mode (FMM) vs. software tiering and how #ComputeExpressLink (#CXL) Type-3 memory boosts in-memory database performance. Read more: bit.ly/4bm0bQ2

#CXLConsortium is looking forward to joining industry leaders at the Xcelerated Compute Show in New York on March 23–24 to discuss how #CXL enables memory pooling, composable infrastructure, and improved resource utilization for #AI workloads. Learn more: bit.ly/40Ni314

#AI #datacenters are evolving to support increasingly demanding workloads. A new collaboration between @SKTelecom and Panmnesia highlights how #CXL enables flexible connectivity between processors, accelerators and memory. Read more via Storage Newsletter: bit.ly/4rjs2pO

#CXL Mini-DevCon is a unique opportunity for #CXLConsortium members to participate in CXL technical trainings, view available products in the ecosystem via our expanded Exhibit Hall, and network with industry peers. Learn more: bit.ly/4bttRf6

The #CXLConsortium is heading to Xcelerated Compute in NYC (March 23–24) as an Industry Partner. Join us to explore the latest advancements in the #ComputeExpressLink (#CXL) specifications and what’s next for AI and HPC. Register with code CXL20: bit.ly/46pqcvV

#ComputeExpressLink (#CXL) 4.0 marks a major advancement, doubling the data rate to 128 GT/s, introducing bundled ports, enhancing memory reliability, and maintaining full backward compatibility. Download the CXL 4.0 white paper: bit.ly/4imaeaL

#CXLConsortium is heading to Xcelerated Compute (NYC, March 23–24) as an Industry Partner. Explore the latest #ComputeExpressLink (#CXL) specification advancements and the future of AI & HPC. Register with code CXL20: bit.ly/46pqcvV

The #CXLConsortium has released the #CXL 4.0 Specification, delivering 128 GT/s bandwidth, bundled port support, and enhanced memory RAS to meet next-gen data center demands. Hear insights on this key specification update in our latest webinar: bit.ly/3YxbVJn

#ComputeExpressLink (#CXL) 4.0 boosts performance, scalability, and reliability for #AI and #HPC workloads. Read the CXL 4.0 white paper for key advancements, including 128 GT/s bandwidth, bundled ports, and enhanced memory RAS: bit.ly/3Z4XZqd

The #CXLConsortium is proud to be an Industry Partner for the Xcelerated Compute show in NYC, from March 23–24. Explore the latest updates to the #ComputeExpressLink (#CXL) specification and the future of AI and HPC. Register with code CXL20: bit.ly/46pqcvV

The #CXLConsortium Compliance Program helps ensure #ComputeExpressLink (#CXL) products deliver reliable functionality and interoperability. Explore the Integrators List to see the growing ecosystem of CXL-enabled solutions: bit.ly/4fauD0j

The #CXLConsortium webinar Introducing the #ComputeExpressLink (#CXL) 4.0 Specification is now on YouTube. Watch to webinar to explore key updates to the specification like 128 GT/s bandwidth, bundled ports, and enhanced memory RAS: bit.ly/4auybKX

The CXL Consortium is proud to participate as an Industry Partner for the Xcelerated Compute show in New York City, March 23–24. Use code CXLCON26 to register and explore the latest advancements in the #ComputeExpressLink (#CXL) specifications: bit.ly/46pqcvV #XCompute

#ComputeExpressLink (#CXL) 4.0 brings major advances for #AI and #HPC workloads, doubling bandwidth to 128 GT/s, enabling bundled ports, and strengthening memory RAS for scalable, reliable next-gen systems. Read the full white paper to learn more: bit.ly/3Z4XZqd

#CXLConsortium members: Join us for an in-person #CXL 4.0 Training Seminar tomorrow in Santa Clara, CA. Experts will deliver a deep technical dive into the CXL 4.0 specification. The event is free for members, but space is limited. Register here: bit.ly/4sJw7FL

Missed the #ComputeExpressLink (#CXL) 4.0 webinar? Our new blog highlights key updates in the CXL 4.0 specification and answers audience questions that we couldn’t cover during the live webinar. Read the blog to learn more: bit.ly/3YJsOAD

#CXLConsortium members are invited to join the #ComputeExpressLink (#CXL) 4.0 technical training seminar for a deep dive into the new features of the CXL 4.0 specification. Learn more: bit.ly/4sJw7FL

As #AI and #HPC workloads grow in scale, #CXL 4.0 delivers key enhancements for next-generation systems. The CXL 4.0 white paper covers doubled bandwidth to 128 GT/s, bundled ports, and enhanced memory RAS introduced in the specification. Read more: bit.ly/3Z4XZqd