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@fclc
@FelixCLC_
Perf & ASM nerd, practical troublemaker Care about clean specs, clean mandates, HPC, IEEE754 & the BLAS. Eng at @ainekk0, prev @tenstorrent, Weather @Canada
Silly goose migrating all over Katılım Ağustos 2011
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I think it’s good that LLMs will pretend to be worse when people yell at them.
kache@yacineMTB
it is laughable how bad gemini is
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This is such a blast from the past of my time at Sun microsystems around folks doing Interval Arithmetic
I Came for the zingers "Floats are Weapons of Math Destruction". Stayed for the HPC engineering at a chip level.
Check it out all you youngsters: posithub.org
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Related, reversal feels like something that isn't discussed as much as you'd think, but a fast version seems like a great option for anyone dealing with networking
@fclc@FelixCLC_
and a portion of the lane/granularity on which you rev is predicated? Effectively, should revs be destructive and shift in 0's to the predicated areas, then reverse? Or should the predication mean that the write back to the destroyed register is blocked?
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Unpleasant truth about programming: solutions that wind up winning aren't the cleanest, most elegant algorithms and design but rather the ones with (morally speaking) the most giant, complete and horrible set of switch statements covering all the weird and interlocking cases.
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Hardware is all fun and games until you run into timing issues, non-deterministic behavior, and over complicated designs to work around stupid bugs.
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@owainkenway Add in corporate reporting and you very quickly understand why accountants are so well compensated for being a mental offload...
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I'm really done with the concept of financial years. You would not believe the sheer magnitude of financial waste they cause, alongside stress for everyone involved.
DOWN WITH FINANCIAL YEARS.
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>spir-v guarantees **4096** ulps of error bound for asin, acos, atan
I'm actually going to disembowel myself
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@thehiphopswami ^ correct opinion for massive machines, if only because the failure mode of networks is so much more common than sockets.
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Disagree. Go to reticle limits! IOs are the bottleneck.
Jim Keller@jimkxa
Recent announcements reminded me of Rent's Rule The IO pins of a device = square root ( gate count ) Small chips don't work, too much IO. Really big chips aren't great either, IO isn't that hard or expensive. Balance :)
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Really liking the design interaction of absolute location predication (instead of the implied dependency of lane size for selection of predicate mask bits)
Also really liking Universal* shift/rotate/reverse
A fun one: what should the behaviour be when a lane bit rev is called
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GTC is basically a bunch of drug addicts begging drug dealers for supply if you replace drugs with GPUs.
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