Marin Ivezic

This Wednesday: I'm teaching SANS SEC529 Quantum Security for Executives at the SANS Cybersecurity Leadership Summit. One day. Virtual. Built for CISOs who need a quantum migration plan - not a quantum physics lecture. Threat models. HNDL exposure. Compliance timelines. Board-ready narratives. Register → sans.org/cyber-security…

🚨 Announcing SEC529: Quantum Security Readiness for Executives A brand-new 1-day course to help CISOs and execs model Q-Day, assess Harvest Now, Decrypt Later exposure, and build a crypto migration plan aligned to NIST PQC and global mandates. 🔗 Learn more and register: go.sans.org/HiDUUO

7/ Full article with the complete discussion: postquantum.com/quantum-system…

6/ The unsexy bottleneck nobody's talking about: a superconducting line costs ~€1,500 today. Material cost? Cents. The gap is yield, labor, and low volume. At scale, that curve collapses - and suddenly cost-per-qubit, not physics, is the story.

3/ But let's be clear: 10,000 physical qubits ≠ Q-Day. Rijlaarsdam estimates 10-100 logical qubits from that. Not breaking RSA. But potentially the first real fault-tolerant computation. That's the milestone that actually matters.

2/ The counterintuitive claim: 3D stacking could improve fidelity. Vertical signal channels are better shielded than crowded 2D planes. Less crosstalk = cleaner operations. If true, this flips the common assumption that "more complex = worse performance."

1/ Today ~90% of superconducting chip area is eaten by wiring, not qubits. That's the actual scaling bottleneck - not qubit physics. QuantWare's VIO-40K delivers signals vertically through stacked chiplets, freeing up qubit real estate. 40,000 I/O connections. One cryostat.

I discussed quantum's modular revolution with QuantWare CEO Matt Rijlaarsdam. The headline: their VIO-40K architecture targets 10,000 qubits by 2028 - not by making bigger chips, but by going vertical with 3D chiplet stacks. The real story is why this matters for the entire industry. 🧵

2/ The counterintuitive claim: 3D stacking could improve fidelity. Vertical signal channels are better shielded than crowded 2D planes. Less crosstalk = cleaner operations. If true, this flips the common assumption that "more complex = worse performance." 3/ But let's be clear: 10,000 physical qubits ≠ Q-Day. Rijlaarsdam estimates 10-100 logical qubits from that. Not breaking RSA. But potentially the first real fault-tolerant computation. That's the milestone that actually matters.

1/ Today ~90% of superconducting chip area is eaten by wiring, not qubits. That's the actual scaling bottleneck - not qubit physics. QuantWare's VIO-40K delivers signals vertically through stacked chiplets, freeing up qubit real estate. 40,000 I/O connections. One cryostat.

"Still only 15" is a nonsense metric. Quantum factoring is not a staircase problem. It’s a threshold problem. Before fault tolerance, bigger demos tell you very little. Rocket development wasn’t judged by whether each prototype flew a few extra meters higher than the last - it was about solving engineering problems to reach the orbit. See: postquantum.com/post-quantum/q… Or if you really want to learn: postquantum.com/post-quantum/c…

@bzogrammer again, x.com/nic_carter/sta… if you think no measurable progress has been made in QC - fidelity, logical/physical cubit count, error detection, coherence, quantum volume in 25 years you are in complete dreamland

Weird I was told quantum computers were theoretical and not ready for prime time

PQC migration is a program, not a patch. I just updated my "Getting Started" list - from "what is the quantum threat?" → "what do we do first?" → "how do we run this like a real program?" postquantum.com/quantum-readin… #PQC #QuantumSecurity #PostQuantum #QuantumReadiness

Switzerland just published its first national quantum strategy. No billion-dollar headline. No national champion. No hype. Just the most honest assessment of where quantum actually stands that I've seen from any government. The big bet: be the CERN of quantum - trusted neutral ground, not another player in the "race." postquantum.com/industry-news/… #QuantumComputing #QuantumTechnology #Switzerland #QuantumStrategy #Quantum

@IanSmith_HSA @apruden08 Well yea, that’s my point

@infosec @apruden08 May want to skip that one. Regev, Shor's and Optimistic Shor's are all legit. Not that one.

“Cybersecurity Apocalypse in 2026” is back - now tied to the Jesse–Victor–Gharabaghi (JVG) algorithm preprint. I published a technical reality check: postquantum.com/security-pqc/c… My take: another day, another (very) unfounded quantum cyber‑apocalypse claim. #quantum #quantumsecurity #pqc

I would trust your understanding more than mine. But just to challenge you a bit: the way I understand IBM's approach, it has two distinct roadmaps (current ones, forget previous ones). One is the "quantum advantage" roadmap. The 120-qubit processor you reference is Nighthawk, which features a square lattice and is explicitly designed for near-term utility using classical error mitigation, not full error correction. Nighthawks will indeed be clustered, but only to push pre-fault-tolerant boundaries. This will allow IBM to provide larger problem-solving capacity in the near term while focusing on the second, technologically more ambitious roadmap - the "Fault-Tolerant" roadmap based on building new, self-contained fault-tolerant modules and connecting those. (New) Kookaburra is the key part of the "Fault-Tolerant" roadmap. (The 1,386-qubit Kookaburra was indeed part of the legacy roadmap.) Due to the qLDPC BB codes, IBM redefined the architecture. Kookaburra is now a self-contained fault-tolerant module comprising roughly 400 physical qubits - 288 for memory block (144 data + 144 syndrome-check) for 12 logical qubits + ~90-100 qubits for integrated LPU. Kookaburra is natively running qLDPC codes, rather than clustering smaller 120-qubit utility processors (Loon (~112 physical qubits) is strictly an experimental testbed used to prove the complex 3D vertical routing and long-range "c-couplers" required for these BB codes.) The ultimate fault-tolerant scale out plan is, in my understanding, to build the 200-logical-qubit Starling system by 2029, not by linking 120-qubit chips together but by networking multiple (18?) ~400-qubit qLDPC Kookaburra modules using l-couplers. For those then to act as nodes in a larger quantum datacenter. I can only go based on their announcements and papers. So please correct me if I'm misunderstanding anything.

@infosec I thought (after speaking with IBM team) that their scaleout strategy was to interconnect small chips not exceeding 120 physical qubits. First scaling level if to put multiple chips on a single chiplet. then mw flex interconnect.

I promised a deep-dive on the Pinnacle Architecture paper after my initial analysis. Media's still running hype cycles. If you want to understand what was actually achieved, and why it's strong research even if Q-Day isn't tomorrow - read on: postquantum.com/post-quantum/p…

Hey. Thanks for the careful read! Kookaburra is still in play, but now with redefined architecture. The 1,386-qubit Kookaburra was from the previous roadmap. The new roadmap built around bivariate bicycle qLDPC codes retains Kookaburra as a modular qLDPC unit ~400 physical qubits per module. Loon (112 qubits, not 120 - you may be thinking of Nighthawk, which is on the separate roadmap and has nothing to do with qLDPC) is the experimental testbed validating the c-coupler connectivity and six-way qubit coupling needed for bicycle codes. Maybe my next weekend should be spent trying to make sense of all IBM's roadmaps...

@infosec "IBM’s Kookaburra processor, expected in 2026, will be the first QLDPC-native module with 1,386 qubits per chip" : sure about that? I thought IBM's plan is to use only Loon architecture chips with 120 physical qubits, and interconnect them (on chiplets or with mw flex).