Marc

$SPY Put Volume spiked on Friday. Previous spikes came close to marking bottoms for the S&P 500. Will this time be different?

$RHM ja, deze ga ik short als die onder EMA50 week sluit straks.

De Nederlandse regering zal gedwongen worden de visionaire leegte waarmee men nu denkt de wereldproblematiek weg te wensen te vervangen door een strategie omtrent het eigen gas en bijbehorende energie onafhankelijkheid. De wal keert het schip wel, al had ik liever gezien dat er iemand in de stuurhut zat en we mijlenver van de kust waren gebleven.

BREAKING: The Securities and Exchange Commission is preparing a proposal to eliminate the quarterly earnings report requirement and instead give companies the option to share results twice a year, per WSJ

UNDEFEATED.

OPERATION EPIC FURY • Destroy Iran’s missile arsenal. • Destroy their navy. • Ensure they NEVER get a nuclear weapon. Locked in.

Next-Gen HBM Thickness Relaxation Gains Momentum… A Blow to Hybrid Bonding Major semiconductor companies are reportedly in discussions to relax the thickness standard for next-generation high-bandwidth memory (HBM), which requires 20-layer stacking. Figures ranging from 825 to 900 micrometers (μm) and above are being floated — surpassing the 775μm thickness of HBM4 (6th-generation HBM), which is set for full commercialization this year. According to ZDNet Korea's reporting as of the 6th, participants in JEDEC (the Joint Electron Device Engineering Council) are actively discussing a significant relaxation of thickness standards for next-generation HBM. Next-Gen HBM Thickness Standard: Discussions Reach 825–900μm and Beyond HBM is a next-generation memory built by vertically stacking multiple DRAM dies and connecting them via microscopic bumps. Through HBM3E, the thickness standard had been held at 720μm, but it was raised to 775μm with HBM4, largely due to the increased stack count of 12 and 16 layers — up from 8 and 12 in the previous generation. Now, the industry is discussing further relaxation of thickness standards for next-generation HBM — namely HBM4E and HBM5 — which will stack DRAM in 20 layers. The figures currently under discussion range from 825μm to over 900μm. Should the standard be set above 900μm, the increase would substantially exceed any prior jump. "JEDEC needs to finalize key standards one to one-and-a-half years before a product reaches commercialization, so discussions around next-gen HBM thickness are very active right now," said one semiconductor industry official. "Figures above 900μm are already being thrown around." JEDEC is the international standards body for semiconductor products. Its membership includes memory companies such as Samsung Electronics, SK Hynix, and Micron, as well as major global semiconductor firms including Intel, TSMC, NVIDIA, and AMD. Historically, the industry has been extremely strict about limiting HBM thickness increases. If HBM were allowed to grow thicker without constraint, it would become increasingly difficult to match the thickness of system semiconductors — such as GPUs — that are integrated horizontally alongside it. Excessive spacing between DRAM layers also lengthens data transmission paths, degrading performance and efficiency. As a result, memory companies have pursued a range of technologies to keep HBM thin, most notably thinning processes that grind down the backside of core DRAM dies, and bonding technologies that reduce inter-die spacing. Both Memory and Foundry Players Want Thickness Relaxation Despite these efforts, there are two primary reasons why the industry is now actively discussing relaxing the thickness standard for next-generation HBM. The first is the shift to 20-layer stacking. Existing thinning processes and inter-die bonding technologies are approaching their limits in terms of how thin HBM can realistically be made. The packaging roadmap of TSMC, a leading foundry, is also a contributing factor. TSMC currently holds a near-monopoly on 2.5D packaging (CoWoS), which integrates HBM and GPUs into a single AI accelerator. CoWoS uses a wide interposer inserted between the chip and substrate to enhance packaging performance. TSMC's next step beyond 2.5D packaging is SoIC (System-on-Integrated Chips), which vertically stacks system semiconductors at extremely fine pitch in a true 3D configuration. In AI accelerator applications, TSMC-SoIC would combine the stacked system semiconductor with HBM. When TSMC-SoIC is applied, the thickness of the system semiconductor increases by tens of micrometers or more beyond the current 775μm baseline — making a corresponding relaxation of HBM thickness standards essentially inevitable. NVIDIA and Amazon Web Services (AWS) are among the companies reportedly planning to adopt TSMC-SoIC. "The need for next-gen HBM thickness relaxation isn't coming from memory suppliers alone — foundry players have a stake in it too," said one industry official. "It's too early to say definitively whether it will be adopted, but discussions are clearly happening among major players." Industry: "Demand for Hybrid Bonding Could Decline" Industry observers interpret these discussions as a factor that could slow the adoption of next-generation bonding processes such as hybrid bonding. Bonding refers to the process of joining individual DRAM dies within an HBM stack; currently, the dominant method is TC (thermocompression) bonding, which uses heat and pressure. Hybrid bonding directly joins the copper interconnects of chips and wafers, eliminating the bumps between DRAM layers and effectively reducing inter-die spacing to near zero — making it highly advantageous for reducing overall HBM package thickness. However, hybrid bonding is technically extremely challenging. It requires: complete removal of microscopic surface contaminants to achieve seamless chip-to-chip bonding; CMP (chemical mechanical planarization) to achieve a perfectly smooth chip surface; and high alignment precision to ensure accurate mating of each copper pad. Yield can also drop sharply when bonding all 20 dies in sequence. As a result, while major memory companies have continued to research and develop hybrid bonding, none have yet applied it in mass production of HBM. Even Samsung Electronics — the most aggressive developer of hybrid bonding — is only expected to incorporate the technology partially, and at the earliest in HBM4E 16-layer configurations. In this context, if next-gen HBM thickness standards are relaxed, memory companies are likely to continue mass-producing HBM using TC bonders. "There's a view in the industry that even a 50μm relaxation in HBM thickness would be sufficient to enable 20-layer stacking," said one industry official. "And since introducing hybrid bonding would require full replacement of existing equipment at enormous cost, my understanding is that memory companies are broadly in favor of relaxing the next-gen HBM thickness standard."