通斯
359 posts



让AI给我解释了一下: 传统芯片升级(摩尔定律)的“老路”是这样的: 想让芯片更快、更省电、塞更多晶体管 → 必须把晶体管画得越来越小(从10nm → 7nm → 5nm → 3nm → 2nm……)。 “画”这么小的线条,只能靠超级贵、超级难的光刻机(尤其是EUV极紫外光刻机)。 每下一代节点,光刻机都要升级,成本爆炸(一台EUV光刻机上亿美元),设计预算也上10亿刀。 华为以前被卡脖子,就是卡在这里——拿不到最先进的光刻机,就没法继续“横向缩”。 LogicFolding完全换了一条赛道: 它不缩小晶体管,而是把同一代工艺(固定节点)的电路,像折千层饼一样竖着叠起来! 还是用原来的晶体管大小(不需要新光刻机去画更小的图案)。 把关键的逻辑电路、内存、模拟电路拆开,一部分放在上层硅片,一部分放在下层硅片。 用超级密的“垂直电梯”(混合键合,1.5微米间距)把上下层直接焊在一起。 结果:信号走直达电梯,不用在平面上绕远路 → 线短了30%,RC寄生小了,频率更快、功耗更低、密度更高。


🇨🇳Huawei Unveils New Chip Design Approach to Challenge Global Leaders Huawei Technologies said it has developed a new chip design principle called the “Tau Scaling Law,” also referred to internally as “Her’s Law,” aimed at advancing semiconductor performance beyond the limits of Moore’s Law. Speaking at the 2026 IEEE International Symposium on Circuits and Systems in Shanghai, Huawei semiconductor chief He Tingbo said the approach could reduce signal delay and improve transistor density to sustain gains in computing power. Huawei said the first Kirin chip based fully on the new design method will be used in a flagship smartphone launching this year, and that the company could reach 1.4-nanometer chip capabilities by 2031. #CHINA #TECH #AI #HUAWEI (mktnews.com/flashDetail.ht…)
























