aog T

143 posts

aog T

aog T

@Taog_1575

Katılım Nisan 2025
33 Takip Edilen62 Takipçiler
aog T
aog T@Taog_1575·
16. Logicfolding挑戰 Fab 朋友跟我說,2um以下HB挑戰的是Oxide to Oxide的bond area,因為pitch減少,代表Ox to Ox或Cu to Cu正確結合面積也變困難,這也反映到小chip的Kirin晶片會先使用,然而給AI晶片使用到大晶片的Ascend在華為此次paper提到要到2030,intra 和local的結合精準度仍是yield挑戰。
中文
0
0
3
603
aog T
aog T@Taog_1575·
15. 再來是他們目前還是覺得積熱最棘手,所以他說今年A20 Pro Chip 的封裝將看到跟以往不一樣的選擇,也與華為的Logicfolding站在對立面。(他強調只有在high end 的Pro晶片將看到這種封裝) 所以在已有製程還能繼續往下做的情況下,他們目前沒有動力使用這種封裝方式。
中文
1
0
0
326
aog T
aog T@Taog_1575·
1. 什麼是Logic Folding? 本質即為使用hybrid bond的3D封裝,但特點是hybrid bond 的bond pitch很高,盡量消除掉繞線距離,如附圖 (這張圖很重要,等等的power/speed會在提到一次)。
aog T tweet media
中文
3
4
27
2.8K
aog T
aog T@Taog_1575·
Tonight, I will summary 4 points on Huawei Chip. 1. TM metal transfer from Al pad to Cu RDL for HB pitch 2. The density on Huawei roadmap and what is the 1.4nm reference to? 3. SMIC develop roadmap 4. Insight from my AP fab and apple design team friends on “logicfolding “
English
2
1
8
793
aog T
aog T@Taog_1575·
The reason is HR is reviewing that TSMC employee’s paid is too high (at least in Taiwan). Even PMD got S-, job grade 33 can get ~100K US dollor which is higher than manager paid in other company. New and shocking company policy will also be announced this year later XD
Jukan@jukan05

To be precise, they say 原因不公開. The speculated reasons seem to fall into four broad categories: Cost burden from U.S. fabs / overseas expansion Higher capex / investment burden from new technologies Prioritizing shareholder returns and dividends Some internal reason they supposedly can’t disclose.

English
1
2
8
1.7K