Underfox

Researchers have developed a new simulator to predict the throughput of basic blocks of all Intel Core μarchs released in the last decade, demonstrating to be more accurate than the predictions of state-of-the-art tools by more than an order of magnitude. arxiv.org/pdf/2107.14210…

Nothing that Huawei has presented was groundbreaking to those truly familiar with semiconductors; even the LogicFolding strategy is not really big news. In fact, DARPA has been testing this strategy since 2017 in the FRANC program. top500.org/news/darpa-pic…

Even when the pulse repetition frequencies of all terminals are the same, the proposed scheme can utilize the slight random drift between terminals to recover high-fidelity information.

The results show that the proposed scheme has wide frequency adaptability, which allows it to separate mixed signals with modulation-rate differences ranging from several million hertz to a few hertz.

Researchers have experimentally demonstrated a single-photon Fourier transform scheme that exploits the implicit correlation shared in photon stream to separate mixed weak signals with high fidelity against extreme environments. #optics arxiv.org/pdf/2605.23611

"On pure performance when normalized on the SIMD/Vector length MCv3 on its peak efficiency point (16 cores) achieves 46% performance of Intel Sapphire Rapids server and 91% performance of NVIDIA Grace CPU superchip."

The evaluation results show that the SG2044 more than doubles single-core performance and improves scalability compared to SG2042 (MCv2).

In this brief paper is presented Monte Cimone v3, the third iteration of the Monte Cimone RISC-V HPC cluster, showing that commercially available RISC-V compute nodes are closing the gap with their competitors in the HPC segment. #HPC arxiv.org/pdf/2605.22831

As I said before, expectation based on hope is a really funny thing. If a turkey's life were analyzed by a chart, the forecast for the day it was taken to the slaughterhouse would be a wonderful day. Thanksgiving is coming and there will be no mercy for the fatty AI ​​turkeys.

@IanCutress @imec_int @MarvellTech Since they made a <periodic table> with the partners, it wouldn't hurt to separate them by specific families and types of partnership.

@imec_int @MarvellTech Partners.

It's @imec_int ITF World 2026!

@IanCutress @imec_int I've seen some patents mentioning the use of 3D photonic interconnects, with intensive use of TGV on glass substrates, but it's still an early development. Indeed, we'll probably only have good news on this point by the end of the decade.

@imec_int Imec on photonic interconnect over the next decade. The push to 3d optics by 2040

These results provide an experimental pathway to experimenting with time-interfaces, generating photonic time-crystals and exploring new regimes of light-matter interaction in time-varying media.

To do this, it was used a powerful few-femtosecond laser pulse to induce order-unity variation in the refractive index of Indium doped Cadmium Oxide (CdO) samples, and probe it with an infrared probe pulse for which the induced index change is in the deep sub-cycle regime.

In this paper, researchers have presented the first experimental observation of time-reflection at optical frequencies. arxiv.org/pdf/2605.15632

The evaluation results show that sampling intervals below 50 ms are sufficient to keep expected gate errors from decaying charges during the hold phase below 10^−4, indicating that the multiplexing scheme is compatible with high-fidelity operations.

In this paper, researchers demonstrated a quantum processing unit that combines a surface ion trap with a time multiplexer via a sample-and-hold technique that initially charges electrodes to fixed voltages and disconnects them during qubit operations. arxiv.org/pdf/2605.16010

The proposed approach reduces the latency and area overhead, improving the overall hardware’s area efficiency by 2.67x compared to the state-of-the-art.

The architecture performs MAC operations using XNOR computation optimized for binary neural networks. By integrating a full adder between in-memory multiplication cells, the proposed design achieves a 50% reduction in routing complexity.

In this paper is presented a novel architecture utilizing a 10T SRAM cell for XNOR-based in-memory computing, aimed at mitigating the extensive routing challenges typically encountered in conventional in-memory computing systems. arxiv.org/pdf/2605.16161

Finally, TTP supports both DFS- and BFS-based traversal, offering a new performance optimization opportunity by selecting different traversal algorithms for different workloads.

The results show that TTP achieves 1.48x speedup on average compared to the baseline, with nearly negligible hardware overhead. TTP also achieves 98.92% average L1 accuracy, which is the ratio of the prefetched blocks being actually referenced by demand loads.

Researchers have proposed tree traversal prefetcher (TTP), a low-overhead, accurate hardware prefetcher for GPU accelerated ray tracing, leveraging the readily available traversal stack in hardware to accurately prefetch BVH tree nodes in a timely manner. arxiv.org/pdf/2605.16253