IEEE Symposium on VLSI Technology and Circuits

#VLSI2026 highlight – Intel 18A-P Advanced RibbonFET 18A-P is design-compatible w/18A. (T1.2, “Intel 18A-P CMOS Technology Enhancement Ft. Advanced RibbonFET (GAA) Transistors & PowerVia for High-Performance Computing,” A. Bowonder, et al, Intel)/Part 3 vlsi26.mapyourshow.com/8_0/sessions/s…

#VLSI2026 highlight – Intel 18A-P Advanced RibbonFET (GAA) Technology With more logic VT pairs, skew corner tightening, new low power & high-performance devices, lower thermal resistance, 18A-P has 9% iso-power performance gain, (>18% efficiency)/Part 2 vlsi26.mapyourshow.com/8_0/sessions/s…

#VLSI2026 technical highlight on Advanced CMOS Technology Intel 18A-P Advanced RibbonFET (GAA) Technology – Intel will present the first performance enhancement in their 18A technology family. /Part 1 vlsi26.mapyourshow.com/8_0/sessions/s…

#VLSI2026 "JFS1 | Quantum Computing & Cryo-CMOS" Part 3 • JFS1.4 | Cryo-CMOS sub-1K 16nm FinFET DAC for Fast Two-Qubit Gates in Spin Qubits vlsi26.mapyourshow.com/8_0/sessions/s…

#VLSI2026 "JFS1 | Quantum Computing & Cryo-CMOS" Part 2 • JFS1.3 – A Cryo-CMOS Fully-Integrated Superconducting Qubit Reflectometry Readout IC w/FCNN-Based Adaptive Drift Mitigation & FIR-DSM-Based Stimulus TX vlsi26.mapyourshow.com/8_0/sessions/s…

#VLSI2026 Joint Focus Session "JFS1 | Quantum Computing & Cryo-CMOS" Part 1 • JFS1.1 – Developing a quantum computer with electrically driven spin qubits (Invited) • JFS1.2 – Detecting Quantum Errors with Hardware-efficient Checks (Invited) vlsi26.mapyourshow.com/8_0/sessions/s…

#VLSI2026 luncheon talk – “Innovative Neurotechnologies – A Journey from the Lab to the Clinic and Back” by Dr. Madjid HiHi, CEA-Leti The CEA-Leti Clinatec biomedical center exemplifies the power of translational ecosystems that advance neurotechnology. vlsisymposium.org/luncheon/

#VLSI2026 Early Registration is open until May 17! The 2026 IEEE/JSAP Symposium on VLSI Technology & Circuits is a live event w/OnDemand sessions afterwards. Plan ahead so you won’t miss participating in conversations driving the future. Register here: vlsisymposium.org/attendees/regi…

#VLSI2026 Satellite – 2026 Spintronic Workshop on LSI (June 14), held at the Hilton Hawaiian Village, will focus on spintronics technologies for LSIs w/high performance & ultra low power. Papers on current status, prospects, & challenges will be presented. cies.tohoku.ac.jp/2026_Spintroni…

#VLSI2026 – The 2026 Silicon Nanoelectronics Workshop is held alternately between Hawaii and Kyoto. Original papers on semiconductor materials, devices, technologies, & applications, or novel materials on silicon substrates are welcome./Part 2 snw2026.conf.nycu.edu.tw

#VLSI2026 will feature a satellite workshop – the IEEE Silicon Nanoelectronics Workshop 2026 (June 13-14), held at the Hilton Hawaiian Village in Honolulu, HI and sponsored by the IEEE Electron Device Society/Part 1 snw2026.conf.nycu.edu.tw

#VLSI2026 Circuits Short Course/Part 2 – “AI-Driven Design Acceleration: Learning Across Circuits, Technology, & Yield” – AI Ass't for AI Analog IC Design, Machine Learning in Diagnosis, Future of Chip Design, & General Transformation Re-engineering VLSI. vlsisymposium.org/short-courses/

#VLSI2026 Circuits Short Course /Part 1 – “AI-Driven Design Acceleration: Learning Across Circuits, Technology, and Yield” will examine Analog EDA, AI for Memory Development, Agent AI in EDA, Practical AI-Driven Floor Planning... vlsisymposium.org/short-courses/

#VLSI2026 Technology Short Course/Part 2 – Continued – Beyond 6F2 – Scaling Frontiers and Future DRAM, Emerging NV Memories, Oxide Semiconductors for 3D Integration, and Advanced Optical Interconnects for AI Computing. vlsisymposium.org/short-courses/

#VLSI2026 Technology Short Course/Part 1 – “Technologies Shaping the Future as Key Enablers for AI” will cover Advanced Logic Technology Scaling, 3D Augmented Dimensional Scaling, Heterogeneous Integration, Material/Process Integration Innovations for AI vlsisymposium.org/short-courses/

#VLSI2026 Workshops/Pt 2: • Design, System & Cross-Technology CoOptimization for Si Spin Qubits • HP CMOS for DRAM: Enabling Mobile, Graphics, Datacenter, & HBM in AI Era • VLSI Device Manufacturability: Improving Semiconductor Yield Thru Virtualization vlsisymposium.org/workshops/

#VLSI2026 Workshops/Part 1: • Advances in Cryo-CMOS: Devices, Circuits & Applications • Embedded Memories in Sub-2nm Era: SRAM Scaling Perspectives, Alternatives, & 3D Futures • Combining Light & Logic: Electronic–Photonic Co-Design for HP Systems vlsisymposium.org/workshops/

#VLSI2026 Plenary speaker 4 – "Meeting AI Demand Through Equipment Innovation & AI-Driven Manufacturing: Progress & Challenges" by Mr. Yoshinobu Mitano, VP Corporate Innovation Division, Tokyo Electron Ltd. Complete plenary information available here: vlsisymposium.org/plenary-sessio…

#VLSI2026 Plenary speaker 3 announced – "Intelligence Accelerated: Memory Innovations to Power the AI Era" by Dr. Nirmal Ramaswamy Corporate Vice President, Micron Technology Complete plenary information here: vlsisymposium.org/plenary-sessio…

#VLSI2026 Plenary 2 speaker announced – "Advanced Package for Next-Generation AI System Scaling" by Dr. L.C. Lu, Senior Fellow and Vice President, R & D / Design & Technology Platform, TSMC More information here: vlsisymposium.org/plenary-sessio…