Gus Smith

another way to think of it: post 1 = structural Verilog, post 2 = behavioral Verilog

wrote a pair of PLSE blog posts explaining the basics of Verilog syntax (post 1) and semantics (post 2) for a PL audience: syntax: uwplse.org/2024/02/19/ver… semantics: uwplse.org/2024/07/22/ver… feedback welcome! from a PL perspective, Verilog is fascinating.

@AartBik @KaewGB thanks aart!!! to you and penporn both! the prolonged google internship was a wonderful chapter of my phd :)

I am very proud of my former intern who I hosted together with @KaewGB

FYI: I'm looking for industry research jobs!!!!!! i will be going on fellowship, and will be available to start in summer 2025.

i defended! if you'd like to learn more about the automatic generation of compiler backends from models of hardware, check it out: youtube.com/watch?v=ePPksg…

@schowdhary02 i also gave a talk on this at PLARCH last summer: youtube.com/watch?v=IkdRtg…

@schowdhary02 in the past was Glenside, which models deep learning accelerator computations as program rewrites, and using those rewrites to find places to invoke the accelerator: orig paper: arxiv.org/abs/2105.09377 used in a larger project: arxiv.org/abs/2203.00218

Writing a compiler for every new heterogenous device is a pain and mostly reinventing the wheel. How should one go about automatically generating a compiler for any new accelerator?

@schowdhary02 please do! my email is on my website.

@gushfsmith Oh wow, I'd love to learn more about your work. If interested, I can invite you to present your work at AMD Research(now RAD).

app readers: lookout for my longtime mentees Andrew Cheung (ninehusky.github.io) and Vishal Canumalla (vcanumalla.github.io) who have experience w/ - paper writing, eval building - ML *and* hardware compilers - prog. synth. - eqsat (bonus: they're just plain good people!)

If you’re at SPLASH, come to my talk on Wednesday morning! I’ll be sharing our new DSL for rule inference- I’m really excited about this work and looking forward to hearing what people think of it 😁

Great talk by @sorawee_p about expressive pretty printing!!

@PLDI @ISCAConfOrg @ben_kushigian @vcanumalla @ztatlock by the way -- both Andrew (ninehusky.github.io) and Vishal (vcanumalla.github.io) are applying for PhDs this year. it's been a joy to work with them both over the past few years, and they will both make stellar PhD students. be on the lookout for their applications!

Generate Compilers from Hardware Models! youtube.com/watch?v=IkdRtg… the video of my talk at the 2023 PL for Architecture workshop (@PLDI /@ISCAConfOrg ) is up! thanks to my coauthors @ben_kushigian, @vcanumalla, Andrew Cheung, René Just, and @ztatlock & the PLARCH organizers!

Andrew's handle is @ninedawg !

@cyberjestr @PLDI @ISCAConfOrg @ben_kushigian @vcanumalla @ztatlock if you consider the junior students obliged to work with me "disciples" 😆

@gushfsmith @PLDI @ISCAConfOrg @ben_kushigian @vcanumalla @ztatlock Intersting talk and idea! Found any disciples yet?

I’m excited to share that our paper “Equality Saturation Theory Exploration à la Carte” will appear at OOPSLA 2023! 2023.splashcon.org/details/splash… In this paper, we propose Enumo, a new DSL for theory exploration.

@notypes and I are starting a brand new stream: TheForkJoin! First stream will be THIS SATURDAY (July 15th) at 10am PT. 🗓️: rb.gy/wpv8a tv: twitch.tv/theforkjoin This time we'll chat with @shwestrick about making parallel functional programming wicked fast. (1/2)