luke k.c. leighton

@iamneubert advance warning: i've read 1,000+ sci-fi and fantasy books and seen every sci-fi film worth watching: the theme's similar to The World's End, I Robot, 1984, Chapp1e, Ghost In The Shell and there's hints of "Elysium". in short: for sci-fi afficionados it'd need to be REAL special

🎬 Trailer: Genesis (Midjourney + Runway) We gave them everything. Trusted them with our world. To become enslaved - become hunted. We have no choice. Humanity must rise again to reclaim. Images: Midjourney Videos: #Runway Music: Pixabay / Stringer_Bell Edited in: CapCut

My newsletter has one subscriber. Me. Help me change that over on LinkedIn. Week 1 includes #AI, #biotech, #cleantech, #spacetech, and #semiconductors. Plus a touch of #SciFi. linkedin.com/newsletters/th…

@dcharold awesome that you ref Iain M. Banks Culture Series. it's one of the best most audacious coherent written visions of the future, along-side Asimov, but more accessible (Asimov is very dry) Q: how about an ETHICAL technological future? presently, right now, we live in Orwell's 1984.

indico.cern.ch/event/1231545/ OSSYM2023 at @CERN 5th International Symposium on Open Search deadline is 31st May

@jonmasters @EcoFlowTech @HusqvarnaUSA well jon you could always uprate its motor and enter it into battlebots.

An update on my @EcoFlowTech Blade adventure. It was a disappointing product that launched too early and I’m sad my favorite YouTubers hustled to hawk it without mentioning the flaws. I did some seasonal maintenance and the @HusqvarnaUSA Automower 430X is back out mowing tonight

it took me a while to notice that ARM has special instructions for linked-list-pointer-chasing alastairreid.github.io/papers/sve-iee… however i am delighted to confirm that SVP64 Vector instructions for linked-list-chasing works. @OpenPOWERorg

@karlfreund @tenstorrent karl, raja, what's your take on this? news.ycombinator.com/item?id=244593…

Here is an interview with Raja Koduri, who just joined the @tenstorrent board of directors... cambrian-ai.com/raja-koduri-on…

This is important work! Help ensure it continues by becoming a @BlockchainComns sponsor. [13/13] github.com/sponsors/Block…

This week’s Silicon Salon 4 explored the challenges and offered some insights into solutions at the intersection of cryptography and semiconductor manufacturing. Explore the presentations by Andrew Poelstra, Red Semiconductor, and @cramiumlabs now! [1/13] siliconsalon.info/salon4/

@ChristopherA despite the fact that these are 64-bit ops, multi-issue execution is possible, as is Vector-level Issue which can be far higher. there is no reason why the back-end hardware could be spammed with 16-wide Vector issue. equally an Embedded system could be only 1-wide and save power

@ChristopherA christopher thank you so much for hosting siliconsalon4 and for the opportunity to present. regarding "performance" i didn't feel i answered adequately: first thing to appreciate is i am designing instructions (+sim +unittests) and only then following up with "performance" contd

The @BlockchainComns Silicon Salon 4 event is tomorrow (Wednesday) at 9am PDT until noon. We're bringing together wallet developers and semiconductor manufacturers to talk about the requirements for the next-gen of chips. You can still sign up! [1/5] eventbrite.com/e/silicon-salo…

@ChristopherA by contrast Power ISA like ARM and x86 *already has* carry-flags, and so we did not have to add it in order to create Vector-Vector add: we can just use the *existing* adde and subfe (and chain them). i will be explaining how that also works with shift mul and div.

@ChristopherA ngggh i genuinely appreciate the work that lowRISC is doing, but by going with RISC-V it is really unfortunate that they started from a crippled base (this is well-known, now). news.ycombinator.com/item?id=244593… and had to add carry opentitan.org/book/hw/ip/otb… (contd)

Luke Leighton @lkcl & David Calderwood will overview the missing RISC ISA instructions related to biginteger operations [3/5]. twitter.com/ChristopherA/s…

doing the write-up for OPF ISA WG External RFC ls016 - Integer Twin-Butterfly DCT/FFT "mul-add-sub-shift-imm" libre-soc.org/openpower/sv/t… the number of instructions it replaces is *eight*. and it's in-place. no temp regs. massive savings. @IBMResearch @OpenPOWERorg @GanesanBlue

with many thanks to @NgiSearch and @FundingBox we will be optimising the SVP64 Draft ISA (proposed to the @OpenPOWERorg ISA WG last week) for Search. VectorCamp will be porting VectorScan to SVP64, Vantosh optimising libc6 string/memory routines linkedin.com/feed/update/ur…

SVP64 has now been formally submitted in full to the @OpenPOWERorg Foundation's ISA TWG. Comprising some 150+ pages it needed splitting into five RFCs: ls001 PO9, ls005 XLEN, ls008 setvl/svstep, ls009 SVP64 and ls010 REMAP. libre-soc.org/openpower/sv/r…

@IBM @OpenPOWERorg @NLnetFDN @GanesanBlue @mikeyneuling @antonblanchard @PCzanik @mpc7500v2 @gabor_samu @kanzure @jon_trossbach @jonmasters @blu51899890 @prozacchiwawa

i'm writing up OpenPOWER ISA Working Group External RFCs full-time at the moment, to be proposed for the SFFS subset. right now i'm doing a "summary" document of future Draft Scalar instructions. feedback welcomed. thx to @NLnetFDN @OpenPOWERorg ftp.libre-soc.org/opf_ext_rfc/ls…

@blu51899890 ahh niiice - yes that's fantastic to have an extra justification. and that's also a great page for post-indexed and pre-indexed

@lkcl I'm referring to the first 68020 addr mode here: #2.2.2.%20Extra%20MC68020%20addressing%20modes" target="_blank" rel="nofollow noopener">tack.sourceforge.net/olddocs/m68020… Clearly the displacement/offset component is an overkill for a risc ISA, but the ra + rb * scale (e.g. base + index * scale) is the essence of the mode that has been in play for decades across 68k/x86/arm.

@blu51899890 libre-soc.org/openpower/sv/r… the only saving grace of the majority of those instructions is that 40+ of them are 9-bit XO and consequently fit into about 1/8th of a Primary Opcode. but around half of them can go in a new 64-bit PO area we're *also* proposing...

@blu51899890 ok arcb.csc.ncsu.edu/~mueller/codeo… is: "EA = RA + RB + immediate" which given that immediates are hugely costly, i feel it would be too much. Libre-SOC is already considering putting in a whopping 53 (!) additional LD/ST instructions, to add Post-Increment and Shifted (cont)