luke k.c. leighton

1.6K posts

luke k.c. leighton

luke k.c. leighton

@lkcl

Ethical Libre Software Developer and Advocate Eco-conscious Libre Hardware Designer lkcl@fizzy:~/src/libresoc/soc$ ps auxww | grep "vi " | wc 1510

The World. (Planet Earth) Katılım Mart 2009
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luke k.c. leighton
luke k.c. leighton@lkcl·
@iamneubert advance warning: i've read 1,000+ sci-fi and fantasy books and seen every sci-fi film worth watching: the theme's similar to The World's End, I Robot, 1984, Chapp1e, Ghost In The Shell and there's hints of "Elysium". in short: for sci-fi afficionados it'd need to be REAL special
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Nicolas Neubert
Nicolas Neubert@iamneubert·
🎬 Trailer: Genesis (Midjourney + Runway) We gave them everything. Trusted them with our world. To become enslaved - become hunted. We have no choice. Humanity must rise again to reclaim. Images: Midjourney Videos: #Runway Music: Pixabay / Stringer_Bell Edited in: CapCut
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luke k.c. leighton
luke k.c. leighton@lkcl·
@dcharold awesome that you ref Iain M. Banks Culture Series. it's one of the best most audacious coherent written visions of the future, along-side Asimov, but more accessible (Asimov is very dry) Q: how about an ETHICAL technological future? presently, right now, we live in Orwell's 1984.
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Jon Masters 🏴‍☠️
Jon Masters 🏴‍☠️@jonmasters·
An update on my @EcoFlowTech Blade adventure. It was a disappointing product that launched too early and I’m sad my favorite YouTubers hustled to hawk it without mentioning the flaws. I did some seasonal maintenance and the @HusqvarnaUSA Automower 430X is back out mowing tonight
Jon Masters 🏴‍☠️ tweet media
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Christopher Allen
Christopher Allen@ChristopherA·
This week’s Silicon Salon 4 explored the challenges and offered some insights into solutions at the intersection of cryptography and semiconductor manufacturing. Explore the presentations by Andrew Poelstra, Red Semiconductor, and @cramiumlabs now! [1/13] siliconsalon.info/salon4/
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luke k.c. leighton
luke k.c. leighton@lkcl·
@ChristopherA despite the fact that these are 64-bit ops, multi-issue execution is possible, as is Vector-level Issue which can be far higher. there is no reason why the back-end hardware could be spammed with 16-wide Vector issue. equally an Embedded system could be only 1-wide and save power
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luke k.c. leighton
luke k.c. leighton@lkcl·
@ChristopherA christopher thank you so much for hosting siliconsalon4 and for the opportunity to present. regarding "performance" i didn't feel i answered adequately: first thing to appreciate is i am designing instructions (+sim +unittests) and only then following up with "performance" contd
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Christopher Allen
Christopher Allen@ChristopherA·
The @BlockchainComns Silicon Salon 4 event is tomorrow (Wednesday) at 9am PDT until noon. We're bringing together wallet developers and semiconductor manufacturers to talk about the requirements for the next-gen of chips. You can still sign up! [1/5] eventbrite.com/e/silicon-salo…
Christopher Allen@ChristopherA

Trust in our tech infrastructure goes beyond software. Enter the world of open silicon for cryptographic semiconductors – fostering innovation and security. Join us at the Silicon Salon to dive deep into the foundations of trust!🧵 [1/9] eventbrite.com/e/silicon-salo…

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luke k.c. leighton
luke k.c. leighton@lkcl·
@ChristopherA by contrast Power ISA like ARM and x86 *already has* carry-flags, and so we did not have to add it in order to create Vector-Vector add: we can just use the *existing* adde and subfe (and chain them). i will be explaining how that also works with shift mul and div.
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Christopher Allen
Christopher Allen@ChristopherA·
Luke Leighton @lkcl & David Calderwood will overview the missing RISC ISA instructions related to biginteger operations [3/5]. twitter.com/ChristopherA/s…
Christopher Allen@ChristopherA

Most RISC ISA chip designs are missing instructions allowing for chaining to create vector results for biginteger operation used in cryptography. @lkct & David Calderwood will be talking on this topic at Silicon Salon 4, hosted by @BlockchainComns. 🧵[1/9] eventbrite.com/e/silicon-salo…

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luke k.c. leighton
luke k.c. leighton@lkcl·
@blu51899890 ahh niiice - yes that's fantastic to have an extra justification. and that's also a great page for post-indexed and pre-indexed
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blu (🇺🇦 in NATO)
blu (🇺🇦 in NATO)@blu51899890·
@lkcl I'm referring to the first 68020 addr mode here: #2.2.2.%20Extra%20MC68020%20addressing%20modes" target="_blank" rel="nofollow noopener">tack.sourceforge.net/olddocs/m68020… Clearly the displacement/offset component is an overkill for a risc ISA, but the ra + rb * scale (e.g. base + index * scale) is the essence of the mode that has been in play for decades across 68k/x86/arm.
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luke k.c. leighton
luke k.c. leighton@lkcl·
@blu51899890 libre-soc.org/openpower/sv/r… the only saving grace of the majority of those instructions is that 40+ of them are 9-bit XO and consequently fit into about 1/8th of a Primary Opcode. but around half of them can go in a new 64-bit PO area we're *also* proposing...
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luke k.c. leighton
luke k.c. leighton@lkcl·
@blu51899890 ok arcb.csc.ncsu.edu/~mueller/codeo… is: "EA = RA + RB + immediate" which given that immediates are hugely costly, i feel it would be too much. Libre-SOC is already considering putting in a whopping 53 (!) additional LD/ST instructions, to add Post-Increment and Shifted (cont)
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