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AI Semiconductor Endgame 2026 (Part 1) New Token Economics Computing Paradigm Shifts from GPU Compute to HBM This article starts from the essence of GPU architectural evolution to address a question the market has long worried about: Why must each GPU's HBM memory demand grow exponentially, and why won't this exponential growth in HBM demand stall? It then derives the first principle of token economics under the current architecture: token throughput = HBM size × HBM BW (bandwidth) It also discusses why the GPU ceiling is determined by HBM's two dimensions of progress. The topic of HBM cyclicality has long been controversial. Optimists argue that AI-driven demand is much greater than before, but the market mainstream still believes that previous up-cycles also saw 20%+ annual demand growth — so what's different this time? AI doesn't change the fact that HBM, like traditional DRAM, has commodity attributes. Once capacity expansion at the demand peak meets a downturn, history will repeat itself. We can take the perspective of compute-chip architecture, start from first principles, and unpack and reason through this question: why this time is genuinely different. ——————————————————————————————— History: The Era of CPU Compute For a very long time, we lived in the era of CPU-dominated compute. The CPU's top-level KPI was performance — running faster — and so each generation of CPUs deployed every method imaginable to push benchmark scores higher. First it was rising clock frequencies, then it was architectural evolution: superscalar designs, and so on. During this period, why didn't DDR need to advance technologically at high speed? DDR3 to DDR5 took a full 15 years. Because in this era, DDR's role was purely auxiliary — and only weakly so. By industry experience, even doubling DDR speed would generally only raise CPU performance by less than 20%. Why did improvements in DDR bandwidth and speed matter so little? Two reasons: 1. CPUs designed all kinds of architectural tricks to hide DDR latency — superscalar designs, wider issue widths, massive ROBs and register renaming to extract parallelism and hide latency, L1 caches, L2 caches — all of which weakened the demand for DDR bandwidth and speed. 2. CPU workloads don't have particularly demanding bandwidth requirements. For most everyday workloads — say, opening a webpage — DDR bandwidth is severely overprovisioned. Even cloud workloads often look the same. In other words, in the CPU era, DDR bandwidth and speed didn't really matter. There was virtually no difference between DDR4 and DDR5 except in a handful of games — and even the JEDEC standard advanced slowly. On top of that, only a small portion of any given app needs to permanently sit in DDR. Whatever is needed can be paged in from the hard drive on demand. App size grew slowly, and so DDR capacity demand grew slowly as well. That's why, over the past decade, the average PC went from 7–8GB of DDR to about 23GB — only 3× growth in ten years. This slow upgrade pace directly affected revenue. Capacity-based pricing was the main way of making money; speed improvements were just a technological upgrade that raised the unit price of capacity. With both of these dimensions advancing slowly, growth could only come from increases in PC/phone unit volumes. So along both dimensions — bandwidth/speed and capacity — DRAM was always a “nice-to-have” appendage to the chip industry. The marginal utility of DDR upgrades was very low, and almost completely disconnected from the CPU era's top-level KPI. ——————————————————————————————— The Paradigm Shift: GenAI's Top-Level KPI When we entered the era of GenAI large models, the computing paradigm shifted, and the top-level KPI changed fundamentally. By the time GPUs evolved into AI inference engines, the top-level KPI was no longer compute alone (TOPS/FLOPS), as it had been for CPUs — it became the cost of a token. Specifically: overall token throughput per unit cost / per unit power. A close second is token throughput speed — because in the agent era, many tasks have become serial, and token output speed has become a critical bottleneck for user experience. This is exactly why Jensen invented the concept of the AI factory: to produce the most tokens at the lowest cost, while pushing token throughput speed as high as possible. In the AI training era, Jensen's economics were TCO (Total Cost of Ownership): the more GPUs you buy, the more you save. In the inference era, Jensen's token economics flip the logic: AI inference has very healthy gross margins, so the logic now becomes: the NVIDIA GPU is the GPU that produces the cheapest token in the world, so the more you buy, the more you earn. The top-level KPI has become a Pareto frontier: along the two dimensions of token throughput and token speed, optimize as far as possible. Each generation of NVIDIA's token factory is essentially pushing the entire Pareto frontier up and to the right. This is the most important KPI of the AI inference era. ——————————————————————————————— From Token Throughput to HBM: The Core Logic Chain Below is the most important logical chain of this article: how to start from the exponential growth of token throughput and derive that the ceiling bottleneck lies in the exponential growth of HBM size and HBM speed. In the era of single-GPU inference with single-thread batch size = 1, token throughput had only one dimension: HBM bandwidth speed. Higher bandwidth = higher token throughput. But once we entered the NVL72 era, inference is no longer single-GPU. It is a system-level token factory composed of 72 GPUs + 36 CPUs, designed to fully saturate HBM bandwidth and compute simultaneously, in pursuit of the ultimate token throughput. Token throughput growth depends on two things: the number of requests batched simultaneously × the average token speed per request. That is: batch size × token speed. Take Rubin NVL72 as an example. At an average token speed of 100 tokens/s, processing 1,920 simultaneous requests yields a token throughput of 192,000 tokens/s. A Rubin NVL72 draws roughly 120kW (0.12MW), so per MW it can handle 1.6M tokens/s. So we need to find ways to push both parameters up: batch size and average token speed. Their product is our top-level KPI — token throughput. Parameter 1: Batch growth — bottleneck is HBM size Every request in the batch carries its own KV cache, which has to live in HBM, with sizes ranging from a few GB to tens of GB. Because hot KV cache must be read at high frequency and high speed at any moment, it must reside in HBM. For a model with, say, 80 layers, every token generation step requires reading the KV cache 80 times from HBM. As batch size grows, hot KV cache grows linearly. And because the hot KV cache for every request in the batch must sit in HBM, HBM size must grow linearly with batch size. Like an airport shuttle bus: the gate wants to move passengers to the plane as fast as possible. If HBM size is small, the shuttle is small, so you have to make extra trips. Conclusion: batch size growth bottlenecks on HBM size growth. Parameter 2: Average token speed per request — bottleneck is HBM bandwidth The decode-phase speed of a large model bottlenecks on HBM bandwidth, because every token generated requires reading the activated weights and KV cache many times over. The emergence of LPUs has, in cases where batch size isn't very large, moved the activated weights portion onto SRAM — but every generated token still requires many reads of the KV cache from HBM. The higher the HBM bandwidth, the faster each token is generated, in essentially linear correspondence. Like the airport shuttle bus: HBM bandwidth is like the width of the door — wider doors mean passengers board faster. The rest of the GPU's configuration is essentially adapted to support batch growth and to keep token compute speed in step with HBM growth. In some cases the GPU even spends excess compute to recover effective bandwidth (e.g., bandwidth compression techniques). —------- To return to the shuttle bus analogy: • Shuttle bus cabin size = HBM Size (capacity): determines how many passengers can fit at once (i.e., how many requests' KV caches can sit in HBM simultaneously). Bigger cabin = more passengers (higher batch size) per trip. If the bus is too small, moving 100 people takes two trips — and total throughput suffers. • Shuttle bus door width = HBM Bandwidth: determines how fast passengers get on and off. A wide door, and everyone piles on at once (decode/token generation is fast). A narrow door, and even with a giant cabin, people queue up and most of the time is spent boarding. • Passenger throughput = cabin size × door-width-determined boarding speed. —------- At this point, we've logically derived the first principle of token-economics hardware demand: Token throughput = HBM size × HBM Bandwidth The top-level KPI of the AI inference era is highly dependent on progress along both HBM dimensions. If we want to maintain 2× token throughput growth per generation, that means each generation of single GPU must grow HBM size × HBM BW speed by 2×! This is the first time in history that HBM memory size can influence the top-level KPI — token throughput. To validate this thesis, we can put NVIDIA's token throughput from A100 to Rubin Ultra on the same chart as HBM size × HBM BW speed. What you find is that the two curves track each other startlingly closely on log axes. HBM size × speed actually grows even faster than token throughput — which makes sense, because HBM defines the ceiling, and in practice utilization of that ceiling is very hard to push to 100%. Even if HBM size × HBM speed grew by 1,000×, with the supporting compute and architecture, it would be very hard to wring out the full 1,000× of headroom. This curve isn't a coincidence — it's the necessary solution of system optimization. throughput = batch × speed. This is the unavoidable first principle of token factory economics. —------- What about software? Won't software optimization reduce bandwidth demand? Reduce HBM demand? This is an independent dimension from hardware. It's like asking: if software on a CPU runs faster after optimization, does that mean the CPU doesn't need to advance for ten years? After all, software is faster now. If that were the case, would CPU vendors still make money? For a CPU vendor to survive, there's only one path: in standardized benchmarks, ignoring software optimization, every new CPU generation must score higher — otherwise it doesn't sell. GPUs are exactly the same. How well software is optimized, and the requirement that the GPU's own token-throughput KPI must improve dramatically every year, are two separate things. As long as token demand keeps growing, the pursuit of higher token throughput will not stop — and so neither will the pursuit of higher HBM size × HBM speed. If HBM size and HBM speed were to slow down, Jensen would personally fly to the Big Three and pressure them to accelerate, because that ishis GPU ceiling. If the ceiling stops rising, can his GPU still sell? Of course, NVIDIA also needs to wrack its brains to extract performance beyond the HBM ceiling through heterogeneous architectural angles. The LPU is a great example — it improved the Pareto frontier substantially from a different angle (the right-hand high-token-speed portion). —-------------------- HBM memory has now bid farewell to that old era of drifting with the tide. On this one-way road paved by exponential demand, it has, in something close to a destined fashion, walked onto the central stage of the industry's epic. When the inference paradigm's first principles evolve to this point, as long as Jensen still wants to sell GPUs, HBM must double — and it must double every generation. This is endogenous pressure from the supply side. It has nothing to do with AI demand, nothing to do with macro cycles, and nothing to do with the moods of the hyperscalers. The only remaining question is this: When demand has been physically locked into exponential growth, will the three players on the supply side — like they have for the past thirty years — once again drag themselves back into the mire of the cycle by their own hands?

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AI半导体终局推演2026(I) 当新token经济学范式从GPU算力转移到HBM 本文从从GPU架构进化路线本质出发，解释这个市场长久以来担心的问题: 每个GPU的HBM内存需求为什么一定会是指数增长，为什么HBM需求指数增长不会停滞? 并推导token经济学在当前架构下第一性原理:token吞吐 = HBM size X HBM BW带宽 同时讨论了，为什么GPU的天花板被HBM的两个发展维度所决定 HBM周期性这个话题争议一直很大，乐观派认为AI带来的需求比以前要大的多，但市场主流仍然认为前几次上升周期也有需求每年20%+增长，这次又有什么不一样呢？AI不影响HBM和传统DRAM一样有commodity属性，一旦在需求顶峰扩产遇上需求下行又会重蹈覆辙。 我们可以从算力芯片架构视角,从第一性原理出发，来拆解和推演一下这个问题：为什么这次真的不一样 ------------------------------- 历史：CPU算力时代 很久以来，我们都处在CPU主导算力的时代，CPU的最高级KPI就是performance，跑的更快，所以每一代的CPU都用各种方法来提高跑分，最开始是频率上升，后来是架构演进superscaler等等 这个时候为什么DDR不需要很快的技术进步速度？比如DDR3到DDR5竟然经历了15年之久 因为这个时期的DDR的角色是纯粹的辅助，而且辅助功能极弱，以业界经验，DDR的速度即便是提高一倍，CPU的performance一般只能提高不到20%这个量级 为什么DDR带宽速度提高了用处不大？两个原因 1. CPU设计了各种架构去隐藏 DDR延迟，比如superscaler，加大发射宽度，用海量的ROB和register renaming来提高并行度隐藏延迟，一级缓存cache，二级缓存cache，削弱了DDR的带宽速度需求 2. CPU workload对DDR带宽要求并不高，大部分日常负载比如打开网页，DDR带宽是严重过剩的，甚至云端负载 也就是说，在CPU时代，DDR的带宽速度是不太有所谓的，DDR4和DDR5除了少数游戏就没啥差别，甚至JEDEC标准也进步缓慢。 另外，绝大部分app需要一直停留在DDR上的部分并不多,需要的时候从硬盘上调度到DDR即可，app的size增长没那么快，导致对DDR的容量需求也较为缓慢。 所以最近十年来，平均每台电脑上的DDR容量大概从7~8GB变成了23GB，十年只增长了3倍。 而这部分升级缓慢直接影响了营收，size容量计价是赚钱的主要方式，速度的提高只是技术升级，提高size的单价，这两个的升级需求都不大，需求主要是随着电脑/手机数量增长而增长 所以DRAM在带宽速度和容量这两个维度上，一直是都是芯片产业锦上添花性质的附属品，DDR升级带来的边际效用是很低的，跟CPU时代的最高KPI几乎没什么直接联系 -------------------------------------------- 而到了genAI 大模型为主导的新时代，计算范式转移让最高级KPI起了根本变化 GPU发展到AI推理的时代，不再像CPU那样只看跑分，最高级的KPI不再是算力TOPS/FLOPS，而是token的成本，特别是单位成本/单位电力下的overall token throuput 其次是token吞吐速度，因为在agent时代，很多任务变成了串行，token吞吐速度成了用户体验的重要瓶颈。 这也是为什么老黄发明AI工厂概念的原因：最低成本的输出最多token，同时尽量提高token吞吐速度 AI训练时代，老黄的经济学是TCO(total cost ownership)，买的GPU越多，省的越多 而老黄在推理时代的token经济学是： AI推理的毛利润很可观，所以逻辑已经转换成：Nvidia GPU是这个世界上让token单价最便宜的GPU，买的GPU越多，赚的越多 最高的KPI变成了Pareto frontier曲线，在提高token 吞吐throughput和提高token速度两个维度上尽量优化 （见图一） NVIDIA 的 token factory 代际进步，其实是在把整条 Pareto frontier 往右上推，这就是是AI推理这个时代最重要的KPI ---------------------------------- 接下来是本文最重要的逻辑链，如何从token吞吐量指数型增长的本质出发，推导出天花板瓶颈在HBM size和HBM 带宽的指数型增长 单卡GPU推理单线程batch size = 1的时代，token吞吐只有一个维度，就是HBM的带宽速度，带宽速度越高，token吞吐越大 但进入NVL72的年代，推理不再是单卡GPU时代，而是72个GPU + 36个CPU整个系统级别的token工厂，把HBM带宽和算力用满，获得极致的token吞吐量 Token 吞吐throughput的增长，依赖两个东西：同时批处理的请求数 X 每个user请求的平均token速度 也就是batch size X per user token 速度 以Rubin NVL72为例，在平均token速度是100 token/s的情况下，同时批处理1920个请求，得到token吞吐量是19.2万token/s 一个Rubin NVL72大概是120KW（0.12MW）的功率，所以得到单位MW能处理1.6M token/s （见图一） 所以，我们需要想方设法提高这两个参数：批处理数量batch size和per user token的平均速度，这两者相乘就是我们的最高KPI，也就是token的吞吐量 ------- 第一个参数：batch size的增长，瓶颈在HBM size 批处理量里的每一个请求req，都会自带kv cache，这部分kv cache是需要存在HBM里的，大小大概在几个GB到数十GB不等 因为hot kv cache是随时需要高频高速读取，所以必须放在HBM里，比如一个大模型的层数是80层，那么每一个token的生成阶段，都需要读取80次HBM里的kv cache 随着批处理数量batch size的增长，会带来hot kv cache的线性增长 又因为这个批处理量的所有请求的hot kv cache，都要放在HBM上，这也就带来了HBM size必须要随着批处理量batch size线性增长 就像是机场接驳车，登机口尽量快的接旅客到飞机，HBM size小了，相当于接驳车size小了，就得多接一趟 结论是：批处理量的数量batch size，瓶颈依赖于HBM size的增长 --------- 第二个参数：每个user请求的平均token速度，瓶颈在HBM带宽 大模型decode阶段的速度，瓶颈取决于HBM的带宽速度，因为每生成一个 token,都要把激活的权重和kv cache 读很多遍 LPU的出现，在batch不那么大的情况下，把激活权重这个部分搬到了SRAM上，但是每生成一个 token仍然要从HBM读很多次KV cache。HBM带宽越高，生成每一个token的速度也就越快，基本上是线性对应的 就像是机场接驳车，登机口尽量快的接旅客到飞机，hbm本身带宽速度就像是接驳车的车门有多宽，门越宽，旅客上接驳车越快 GPU的其他配置，都是在适配batch的增长以及要让token compute的速度配平HBM的增长，甚至会用多余的算力来获得部分的带宽（比如部分带宽压缩技术） —----- 在那个接驳车的比喻例子里 接驳车的车厢大小 = HBM Size（容量）： 决定了一次能装下多少名旅客（也就是能同时装下多少个请求的 KV Cache）。车厢越大，一次能拉载的旅客（Batch Size）就越多。如果车太小，想拉100个人就得分两趟，系统整体的吞吐量就上不去。 接驳车的车门宽度 = HBM Bandwidth（带宽）： 决定了旅客上下车的速度。门越宽，大家呼啦啦一下全上去了（Decode/生成Token的速度极快）。如果门很窄，哪怕车厢巨大能装200人，大家也得排着队一个一个挤上去，全耗在上下车的时间里了。 旅客的吞吐量 = 接驳车车厢容量 x 接驳车旅客上车速度(车门宽度) —--------------------------- 至此，我们从逻辑上推演出了token经济学的硬件需求第一性原理： Token throughput = HBM size X HBM Bandwidth AI推理这个时代的最高KPI，实际上是高度依赖于HBM的两个维度的进步的 如果要维持token throuput每一代两倍的增长，实际上意味着，每一代的单GPU上，HBM size X HBM BW带宽之积要增长两倍！ 这也是历史上第一次，HBM内存的size可以影响最高的KPI token throughput！ 要验证这个理论，可以把Nvidia从A100到Rubin Ultra这几代的token 吞吐throughput，和HBM size X HBM BW 放在同一个图里比较 （见图二） 可以发现，这两个曲线的走势在对数轴上惊人的一致 HBM size x HBM带宽增长的甚至要比token吞吐量更快，毕竟HBM决定的是天花板，实际上这个天花板增长的利用率utilization是很难达到100%的，也就是说，HBM size x HBM 带宽就算增长1000倍，其他算力和架构的配合下，很难把这1000倍的天花板潜力全部榨干 这条曲线不是巧合，而是系统最优化的必然解 throughput = batch × Bandwidth，这就是token factory 经济学最绕不开的第一性原理 —-------- 软件的影响呢？软件的优化会不会降低带宽的需求？降低HBM的需求？ 这跟硬件是独立两个维度的，这好像在问，如果CPU上的软件优化了之后跑的更快，是不是CPU就十年不用发展了？反正软件跑的更快了嘛 这样的话，CPU厂还能赚得到钱吗？CPU想要存活下去，只有一条路可走，在标准benchmark，不考虑软件优化，每一代CPU必须要跑分更高，不然就卖不出去 GPU也是一样，软件优化如何，和自己的token吞吐量KPI每年都要大幅进步，是两回事 只要token的需求继续增长，对token throuput的追求就绝不会停止，那么对HBM size X HBM 带宽的追求也不会停止 如果HBM size和HBM 带宽发展慢了，老黄一定会亲自到御三家逼着他们技术升级，因为这就是老黄gpu的天花板，天花板要是钉死了不进步，老黄的GPU还能卖出去吗？ 当然了，Nvidia需要绞尽脑汁去从异构计算的架构角度榨取HBM天花板之外的部分，比如LPU就是一个很好的尝试，把Pareto frontier从另一个角度改善了很多 （右半边高token速度的部分） —-------------------------------------- HBM内存已然告别了那个随波逐流的旧时代，在这条由指数级需求铺就的单行道上，以一种近乎宿命的方式走到了产业史诗的主舞台中央 推理范式第一性原理演化到这一步，只要老黄还要卖GPU，HBM就必须翻倍，而且必须代代翻倍。这是supply side的内生压力，与AI需求无关，与宏观周期无关，与hyperscaler的心情也无关 剩下的问题，只有一个： 当需求被物理锁定为指数增长的时候，供给侧的三个玩家，会不会还像过去三十年那样，亲手把自己再拖回一次周期的泥潭？

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