Ryan Flaherty
1.3K posts

Ryan Flaherty
@rflaherty71
round 2 Previously Thekla/Google.












Most programmers are taught that L1 is the “top level” cache on x86. It’s not quite true anymore! Intel calls it the Decoded Stream Buffer (DSB), AMD the OpCache. Only enough room for ~4,000 micro-ops, but there are interesting ways to take advantage of it.


Completely untrue. It is the opposite, everything is actually async but your cpu and the kernel tries really hard to sell you a synchronous model.





@SheriefFYI what? it's true. wasn't meant to be a snarky comment about rust superiority or w/e. i just think it's nice that you get this performance-oriented behavior automatically also, if you're manually arranging your struct like this, why not just add the packed attribute?



