singlebeansoup

SiCs blew up during burn in. No clue why. We already did a thermal survey during burn so we knew it wasn’t temp. Started investigating, initial hypothesis was parasitic Miller turn-on causing a shoot through event. I looked at VGS vs. VDS to try to spot any Miller bumps at the gate during turn-off of the low side or high side FET. No cigar. Everything looked good. Eventually found a problem with our test bench interlock switch that applies high voltage to the power module. Although the input supply was soft started, whenever we flipped the switch we’d see a large transient spike on the input close to 2 • VIN, caused by resonance between our input cabling inductance and input capacitance. These would show up as latent failures, we believed. We thought this was the culprit, but it was only a guess. We’ve had FETs blow up since we stopped using the switch too, so it’s back to the drawing board. We had some IRAD budget open up so I’m going to be looking at optimizing the gate drive and power stage to minimize loop inductance that could cause voltage rise at the gate if the off FET, governed by L di/dt. Our di/dt won’t change and it’s a lot, on the order of probably 100a/ns maybe. The L is our gate loop inductance from the gate drive to the gate, to the source through Cgs, from the source back to the gate driver, completing the circuit at the gate. Looking to minimize this loop inductance L. Layout problem, reducing parasitic inductance as much as possible. We’ll see what happens. Doing it on KiCAD too which will be a new one for us, getting it approved by IT for increased speed of design, iteration, fail, design iteration, fail, etc.

@singlebeansoup wow! what is happening? what was the previous leading hypothesis?

hardware is so unforgiving. software is child's play. literally a playground of unicorns and rainbows.

@zackslab Update: still haven’t found root cause

@singlebeansoup you get it

@realwillreil I’m avoiding IPO request due to physiognomy alone

I’m cancelling my Claude subscription, not supporting this blatant attempt at legal monopoly. He would fear monger 3d printers if he had the economic incentive. Morally bankrupt people trying to control who has access to the tools which enable you to compete.

@zackslab Hell yeah

scout sniper Dingo, reporting for duty 🫡

@i2cjak GYATT GYATT GYATT

@MostlyPeaceful You know ball

My favorite spot is in Blue Water Bay LJ Schooners

Going to Destin, FL next week. Where’s a good place to eat or grab a drink?

@i2cjak Chassis symbol for ground? Cmon man

lfg my sticker design came in Half of what I make goes to KiCad!!!

@i2cjak 10Gigashits per Megabit?

@i2cjak Into the wagecage you go

so now I’m working on live cameras for motorsports

@i2cjak We can hear you

@zackslab Hell yeah. Cozy.

kids are sick, it’s cold and windy… i’m making a fire.

@i2cjak Still wageslaving?

happy to announce that I will now be using ALTIUM DESIGNER for the LOW LOW PRICE of $4,000 a YEAR to design 2 layer boards for water heaters etc.

Nice, looks great! I don’t think people realize the complexity behind power supply design and what is happening physically. We’re really lucky to have plug and play solutions for converters, thinking low-voltage/low-power bricks or IC’s. It’s extremely multi-variable, as your app shows.

@singlebeansoup thank you! yes, i've been building out a toy local webapp with a bunch of interactive tools to help build tuition around some of these ideas:

so i think i'm finally starting to understand what slope compensation is. we must first go back a few steps to understand WHY it's even needed. continuous conduction boost topologies have a right half plane zero (rhpz). what is an rhpz? well, it's a zero on the right half of the s-plane. what this manifests as is that the output's first move will be in the WRONG DIRECTON. say you want to deliver more energy to the output. to do this, you must charge the inductor for longer. to deliver more energy, you must save up for it, and while you save, the output is cut off. this is the crux of what makes boost converters shitty to control: you command it, “give the output more current” and its first move is “k, here’s less”. so for this reason, you can’t make the outer voltage loop bandwidth too aggressive (relative to the rhpz), or it’ll start chasing its own tail (oscillate). how do you fix this? you add another loop. a faster (cycle by cycle) peak current mode control loop. this does not REMOVE the rhpz, but it fundamentally changes the control problem. this new "inner loop" allows the outer loop to act on current thresholds instead of acting on the duty cycle. why is this better? because it allows for the outer loop to ask for a more direct, physical quantity (current). instead of asking: “what exact duty cycle should i try right now and pray it behaves?” it can say: “i need this much current and i'll let the inner loop can figure out the duty cycle.” it's a dynamic duo. this makes the slower outer loop’s job simpler by handling ugly cycle by cycle details. it would be great if we were done here, BUT WE'RE NOT. we got cute but we must pay the piper because peak current mode control has its own achilles' heel. say you wanted to boost from 12V to 48V. your duty ratio (in a perfect world) will be 0.75 meaning that 75% of the time, your low side FET is charging the inductor, and 25% of the time, the inductor is discharging through a diode or high side FET. this leads to two very asymmetric inductor current slopes. the up slope (charging) magnitude in this case is 3x less than the down slope (discharging) magnitude. why does this matter? perturbations. wtf is a perturbation? well, the real world isn't kind. your supply voltage might sag. your load might change. these changes can cause the current to start a little too high on one cycle, which means it will hit that threshold a little earlier, so the switch turns off a little earlier. so what? let's play this out. if the switch turns off a little early, that means the inductor will discharge for longer. meaning next cycle, the current starts little too low, which means it will hit that threshold a little later, so the switch turns off a little later... you see where this is going. high, low, high, low, high low... SUBHARMONIC OSCILLATIONS. each cycle, a perturbation is multiplied by the ratio m2/m1, where m2 is the inductor discharge slope and m1 is the inductor charge slope. above ~50% duty cycle, this ratio exceeds 1, meaning perturbations GROW each cycle instead of dying out. the system is geometrically divergent. OKAY THIS IS FINALLY WHERE SLOPE COMPENSATION COMES IN. slope compensation is simply adding an artificial slope ONTOP of the sensed inductor current's charge slope. this changes the ratio from m2/m1 to (m2-mc)/(m1+mc), where mc is the added artificial slope compensation. this new "compensated" slope gets fed into the comparator, changing the comparator’s view of the upslope, making it appear more symmetric with the downslope's absolute steepness. the net effect of this is that the outer voltage loop will find a new equilibrium around this remapping and the comparator stops overreacting to natural perturbations because they die out once mc > (m2-m1)/2. here's an animation i made to illustrate what this looks like:

@zackslab Simplis Elements (free version) my friend

i like how LTspice uses "DEF CON" to indicate the level of convergence difficulty. [Run: 1/1] Simulation Time = 11.2826 ns Transient Analysis 00.0% done. Def Con 2 inter=10 fill-ins=46 this simulation will complete in 8.4 years. time for a new approach.

@DanielBogdanoff Power electronics design for radars and military vehicles

Electrical Engineering Twitter Role Call! If you want a feed full of EE/electronics go though and connect with all the profiles that respond. Add yourself -> post what you do in < 5 words (stealing this idea from⬇️, I love it!)

@BowTiedNiners Forgot to mention LJ Schooners as well. Restaurant and oyster bar on a marina. Not in Destin, in Bluewater on the north side of the Mid Bay Bridge, but that spot is a banger.

@singlebeansoup On the list for sure

Do I have any Floridians who follow me ? What are some cool things to do in Destin?

@zackslab @i2cjak I don’t know much but I’ll try to help where I can

@zackslab @i2cjak Sure thing man

okay rough block diagram, what am i missing? feel free to copy @i2cjak: