Thomas Cowan

Samsung, SK, and Micron Clash Over 16-HI HBM… Nvidia Orders Development Samsung Electronics, SK Hynix, and Micron have entered the race to develop 16-HI High Bandwidth Memory (HBM). This is because Nvidia, the world's largest AI semiconductor company, has requested supply for the second half of next year. The 16-HI HBM is a product that has never been commercialized before, and the company that first solves various technical challenges, such as DRAM stacking, is expected to seize dominance in the next-generation market. According to comprehensive reporting by the Electronic Times on the 28th, it has been identified that Nvidia requested domestic and foreign memory manufacturers to deliver 16-HI HBM by the fourth quarter of next year. Consequently, Samsung Electronics, SK Hynix, and Micron have commenced full-scale development work for the mass production supply of 16-HI HBM. Although concrete contracts have not yet been signed, it is reported that discussions are underway internally regarding even initial production volumes. An industry official familiar with the matter stated, "Following the supply of 12-HI HBM4, a request for 16-HI supply has also been made, so we are establishing a very fast development schedule," adding, "Performance evaluation could begin as early as before the third quarter of next year." Currently, the 12-HI version of HBM4 is scheduled for mass supply early next year, but dealings for the next product, the 16-HI version, have accelerated. Another high-ranking industry official suggested the possibility of it being named HBM4E, saying, "It is likely that the product will be 16-HI HBM4, but the generation or name could change depending on performance and mass production timing." The 16-HI stack is an HBM that the three memory companies have never commercialized. Currently, what is being provided as prototypes to Nvidia and entering mass production is the 12-HI HBM4. Since it is an unprecedentedly high-stack HBM being attempted for the first time in the semiconductor industry, observations suggest that technical challenges will be formidable. Above all, there are concerns about the thin wafer thickness. While existing 12-HI HBM has a wafer thickness of about 50 micrometers (㎛), it is reported that this must be reduced to around 30㎛ to stack 16 layers. The HBM4 thickness standard defined by JEDEC (Joint Electron Device Engineering Council) is 775㎛. It is about 50㎛ thicker than the existing HBM3E (725㎛). This leeway was given because implementing thin HBM becomes more difficult as the number of layers increases. However, the prevailing opinion is that JEDEC will not further increase the thickness for this 16-HI HBM. This means more DRAMs must be stacked within 775㎛. If the thickness becomes thinner, improvements in wafer processing technology are necessary. Technology to cut and polish (CMP) the wafer without breaking it is required. Because of these technical issues, it has been confirmed that some memory manufacturers have introduced new wafer processing equipment. HBM is implemented by vertically stacking and attaching DRAMs, and this bonding process is also identified as a technical hurdle. Since more DRAM wafers need to be attached compared to the existing 12-HI stacks, thinner bonding materials are essential. Currently, Samsung Electronics and Micron are proceeding with the bonding process using Thermal Compression Non-Conductive Film (TC-NCF), while SK Hynix uses Mass Reflow Molded Underfill (MR-MUF). An industry official said, "The current bonding material thickness is around 10㎛, and to stack more DRAMs, this must be reduced to secure competitiveness," adding, "Dissipating the heat generated after bonding is also a challenge." $NVDA