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Wow, lots of new twitter followers just joined. Welcome! Just to give you an opportunity to get to know me and the ZipCPU blog, here's a bit about me and what you can expect here: zipcpu.com/blog/2018/10/0… Again, welcome!
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Zip CPU
7.5K posts
Zip CPU
@zipcpu
FPGA design engineer and blogger, placing particular emphasis on test and formal verification
Gisselquist Technology, LLC, Se unió Ocak 2017
201 Siguiendo8.2K Seguidores
@waskitaadijarto Confusing? Yes. However, this tends to be par for the course when working with soft CPUs on FPGAs. Most of my soft CPU implementations have block RAM (and cache, if space allows), SDRAM, and flash. Not all devices have SDRAM. Not all devices have cache. You have to adjust.
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@zipcpu I am curious. what microcontroller/DSP has SDRAM and block ram? Different types of memories in a microcontroller is important for price & performance, but it's really confusing for the students.
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Progress! After many long hours, I can finally pass a lint check!
Okay, only the memory mapped reads and arbitrary commands are implemented, ... but at least I should be able to simulate the entire design.
Zip CPU@zipcpu
Between planning and building: 1. Plans become promises, goals, and even contracts 2. They can also be used to solicit investment Most of my planning is now done. Let's see how much we can get done on a "day off" / holiday.
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Frankly, we could've gone even faster in our own testing, save that the voltage translation chip we required was limited to 60MHz. The IP itself should go up to 100MHz easily.
Indeed, it's designed to hit the 400MB/s eMMC limit--I just don't (yet) have the hardware to test that
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Let me congratulate @lowRISC on an open source SDIO controller!
Why they left the ASIC bar at 11.1MB/s, though, when you can get close to 47MB/s in an FPGA is a bit beyond me.
arxiv.org/pdf/2603.11849
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When working with digital logic, there are only two possibilities: True and False.
There are no truths "identifying" as falsehood or vice versa. It either works, or it doesn't.
CidCampeador@CidCampeador777
@1llegalEngineer @chiguy892 @zipcpu They fly so close to the silicon, they end up based and redpilled
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Here's a bug from this weekend: In this case, two bugs canceled each other out, leaving me believing the design worked in a configuration that I'd never hardware tested it in.
Also, a good question, how good should a "self-checking" test bench be?
You can read more about this bug here: github.com/ZipCPU/sdspi/i…
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The first (often unwritten) premise, must justify the use of logic in the first place.
zipcpu.com/formal/2021/01…
RamenNoodleNinja@RamenNudleNinja
@chiguy892 @1llegalEngineer @zipcpu Only if their base axioms and assumptions are the same.
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Zip CPU retuiteado
@1llegalEngineer @chiguy892 @zipcpu They fly so close to the silicon, they end up based and redpilled
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3Clk/transfer throughput is *HORRIBLE* throughput performance. That's one of the reasons why I don't use Classic Wishbone, but rather use Pipeline.
A cache, DMA, or whatever else, should be able to get 1Clk/transfer throughput between the cache and external memory.
Marcelo Samsoniuk@samsoniuk
@vadakkodaan @splinedrive of course, the core buses can be really fast: the I-bus can be pipelined for 1 clk/transfer on BRAM but the D-bus not (can do 1 clk/transfer on LUTRAM)… the easy way is use the bridge, that merges them and slow down a little (3 clk/transfer) 🔥
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This performance is pitiful for two reasons.
1. 3 bursts of 4 beats each should only suffer the latency once. This should've been 15 clocks total, not 21.
2. A 3ck latency is a bit much for block RAM. Why not 2ck? (1ck might be a challenge, if we assume it takes a full clock from addr to memory output ...)
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