logic destroyer

I spent all these years experimenting instead of fully pushing a single project through. For example, implementing async FIFOs completely from scratch. And now I can use that knowledge to push my SDRAM controller to much higher clocks. Let’s see what’s possible for my new KianV Stealth 5-stage Linux SoC.

My 5 stage pipeline KianV Stealth CPU is now booting Linux in simulation. For now in interlock mode, no branch prediction, no return address stack, and using the old MMU from my previous SoC. Still, this is a nice milestone. Three weeks ago it was only running bare metal. Looks like this will be a fun summer.

I am now a CDC dude, testing my async FIFO with PRBS to verify my design at any clock ratio, watching the full and empty signals clean on the logic analyzer, trying my circuit on a UL3S FPGA, and if you understand it, it is easy peacy, thanks to Clifford E. Cummings from Sunburst Design. Straight from Compton.

Okay, let's try to make the SDRAM controller support multi-beat bursts.

KianV Stealth Linux RISC-V SoC. First bring-up with a 5-stage pipeline CPU and GShare branch prediction. Running at 25 MHz for now during bring-up, but already timing clean at 50 MHz. Ported my old SoC parts like SDRAM controller and UART to the new pipeline core. Caches are still primitive, memory is single-beat and one clock domain only. Tons of potential left. Fun summer ahead.