asic destroyer

I made my RISC-V ASIC/FPGA KIAN-V implementations open and free for everyone. github.com/splinedrive/ki…

@samsoniuk @CStredicke ☝️

the endian can be a big problem, since it affects not only the layer 3 and 4, but upper layers too! for example, RTP header is endian dependent and even the payload can be endian dependent! thanks God, the DarkRISCV is endian independent and can easily support both! 🔥

fun fact: sometimes I leave this 486 on top of the boards I'm working on, so people who don't know the project think it's powered by a 486! 🤣

fun fact: the Rust programming language isn't yet aged enough to function independently on your system, so never create a user for Rust! otherwise, you'd be legally required to provide Rust's date of birth and face restrictions! 🤣

Google's Gemini learning about DarkRISCV! 🤣

Took a 5-month break from riding (winter, darkness, cold…). Built two ASICs instead. Now back to training and pushing forward on the next SoC. It’s going to be insanely fast. ASICDestroyer 4 life!

meanwhile, inside literally every string you print: while(ptr!=NULL) putchar(*ptr++);

Still a lot of things are happening, like WhatsApp now supports audio through the Vodia integration which is pretty cool for customer interaction

@samsoniuk @ATaylorFPGA WTF, amazing board. I love SDRAM-based boards. Nobody needs that DDR RAM garbage on FPGAs lol. allaboutfpga.com/product/edge-a…

On X, I let loose. On LinkedIn, I’m reserved. The engineer.

Verification is the #ASIC terminology of the week! zerotoasiccourse.com/terminology/ve… In the last month, Verification has been the 25th most popular out of 42 terms.

💪💪💪💪💪💪💪

I set up port forwarding for my @tinytapeout ASIC FPGA emulation for one of the TinyTapeout guys. And as you can see, people immediately started trying to break into my FPGA design.

AI can simulate knowledge, but not intuition.

Hey, hey. Who would have thought? The KianV RV32IMA SV32 Linux SoC runs with X11. What awesome stuff you can do with the #FPGA! :) music by @therealh0ffman #linux #X11 #riscv

@matthewvenn sorry :)

I’ll admit it: when I first saw @mattvenn’s videos in 2021, right when I started with logic design, I thought: who is this crazy guy talking about making chips? I didn’t even really know what chips were. Through @mattvenn, @urish, @PsychogenicTech and @tnt — and @tinytapeout — this world suddenly became accessible. I’m honestly very grateful. Because of them we can suddenly build weird things at the micrometer scale and actually look at what I made on real silicon.

You get three guesses where the KianV SV32 Linux SoC @TinyTapeout design is located.

The next KianV SV32 chip is coming.

A small step for a hobby logic designer, but a giant leap for @tinytapeout. The first official RISC-V uLinux ASIC, yes, ASIC, you heard that right, is operational and functional. Just dabbling in chip design as a hobbyist. Haha, what an awesome achievement! Thanx to @matthewvenn @UriShaked @tnt4all Rebellmike troyburn @PsychogenicTech #tinytapeout #chipdesign #verilog #130nm #Skywater #yosys #openlane @WokwiMakes #logicDesign #logicDestroyer

Logic designers use real machines. Laptops are for software people.