Zip CPU

Wow, lots of new twitter followers just joined. Welcome! Just to give you an opportunity to get to know me and the ZipCPU blog, here's a bit about me and what you can expect here: zipcpu.com/blog/2018/10/0… Again, welcome!

@al__towaijri Send me an e-mail, and I can provide you with instructions.

@zipcpu I can’t seem to find it, all I’ve found is a link to repo which might be private and requires an invite or the repo link is outdated. Could you please point me to the exact post.

ChatGPT can't even design a working AXI-Lite slave. Think it'll realize the bug if I point it out?

@al__towaijri It's still there. It's still available. I still use it.

@zipcpu I was wondering if the full axi formal still available for Patreon subscribers, or if there are other sources to obtain them from.

@gatelevelanon Lord willing, I'm hoping to quadruple that speed.

@zipcpu Sorry it was Megabytes per second . Mega = 1000 , not 1024

Here's what I've been working on today. This is a 2x(1S-4D-4D) configuration. (1S=SPI, 4D=Quad SPI, DDR) It now has a full regression suite, and passes all them all

@alexschultz002 No. It's SimVision from Cadence cadence.com/en_US/home/too…

@zipcpu Is that gtkwave?

Me, 30yrs ago: "Mom, I wanna be an engineer. Why do I have to learn all this English stuffs?" I'm now an engineer. I've spent much of this week writing user guides and responding to customer queries. I guess that's why.

@gatelevelanon QSPI has the advantage of a low pin count over LPDDR5. Even Octal SPI has an advantage. Pin count starts to get expensive in ASIC designs.

@zipcpu QSPI, SRAMs are easy. Real fun(hell) happens on DRAM LPDDR5 and 5x.

@gatelevelanon This particular mode (QSPI/DDR) can do at most 16b/clock, so that's about a 50% throughput. The IP itself can go up to 32b/clock, just not with QSPI. Yes, longer reads will help minimize the impact on latency. Aggressively merging operations is key to throughput.

From a performance perspective, QSPI is not very efficient at short data transfers. In this screenshot alone I can see it barely used 25% of the available bandwidth on actual data transfer. Rest of it was wasted on SPI command sequence and round trip latency. I have extracted 98% efficiency with long data transfers. iirc it is possible to use a single SPI command and receive a long sequence of bytes without interruption.

@gatelevelanon That's a good summary.

I did QSPI performance stuff on some industrial chips many many years ago. Tell me how many of the following did I understand correctly ? 1. An AXI master sent a read request. 2. An AXI slave caught it. Then it was translated to an SPI command sequence and a memory address accessible on that address space. 3. The controller (QSPI) returned 8 x 8 bits x 2 = 16 bytes. I say this because I can only see 8 clock ticks and 8 bits per clock tick. And for dual data rate you multiply it by 2. 4. The 16 bytes were packed into a 4-beat AXI response with 4 bytes per beat, by the AXI slave controller. It sent them to the AXI master. The AXI master received this packet. The completion of the transfer is indicated by RLAST.

@alexschultz002 No need. I've already got a random number. 😆

@zipcpu Looks like that image has plenty of boxes. Keep it open to air and use the EMI for RNG

Hey Dan, I'm thinking of building a PCB with an FPGA, 2x HDMI connectors and 2x GbE connectors. What do you think?

@OSdev_ Adapters and bridges cost latency and logic. Why waste the latency on a critical path, when you could have built the CPU's memory controller to handle arbitrary widths in the first place? It's not that much harder, and there's quite a benefit to doing so.

@zipcpu Hey, what do you mean by point 1 ? In modern SoCs, we can have different widths with an adapter or bridge, right?

Wow ... it's amazing how many unusable RISC-V SOCs there are out there. 1) If you are going to build a CPU, the CPU's memory bus interface should match the width of the memory. (Today's bug.) 2) If you want to use SDRAM, don't use Wishbone Classic.

The width issue continued into RDATA, where it was much harder to see. A 32b signal was attached to a 512b port. Weird thing is, the engineer swore to me this passed all of his testing.

Today's bug of the day helps to highlight why it helps to have an automatic bus compositor. Here we have a CPU try to talk to memory. The memory controller was expecting a 512b data width. It was given 160b of WDATA, and 36b of WSTRB. Connecting WVALID to WLAST was the first to raise my eyebrows, but it's technically not a bug when going from AXI-Lite to AXI.

3) If it can't pass a Verilator lint, find another CPU.

@sergeykhbr Before or after the updates? 😄 Perhaps I should invite the author to share what he's up to on here.

@zipcpu I like this idea very very much

@alexschultz002 I thought an environmental protection (physical) package (i.e. a box ...) might be useful as well.

@zipcpu Need an expansion header for RPi hats

@zacckOS Which MIPI? I've got my fingers into so many MIPI related projects, and each one has a different interface ... yeah.

@zipcpu MIPI input or is that in the FPGA blob?