Zip CPU

Wow, lots of new twitter followers just joined. Welcome! Just to give you an opportunity to get to know me and the ZipCPU blog, here's a bit about me and what you can expect here: zipcpu.com/blog/2018/10/0… Again, welcome!

@Palsenberg @ATaylorFPGA $300 for all 13 servers.

@zipcpu @ATaylorFPGA 300 for 12 servers ? Or per server ?

Today's task: populating a quarter rack (12U) with more CPU power ...

@ATaylorFPGA I purchased 13 CISCO UCS C240 M4 servers for $300. The 12U rack in the picture cost more. My goal is simple: simulations and formal proofs. Whether my wall/house has enough power and cooling for the four I'm planning on putting in the rack is ... yet to be determined.

@zipcpu Very curious what your build includes

Every thing will always work until the customer wants a delivery.

Mmm ... breakfast ...

A crypto engineer once taught me: "The math helps you. The math hurts you."

@soundpwm understands well: "You can't be a good engineer if you can't define good." Well said. 👏

The IEEE code of ethics ... has lost its way. zipcpu.com/blog/2026/07/1…

The second bug will get fixed in RTL: On any NAK, the design should STOP, and wait for S/W, unless told to go back and repeat things. (The go back and repeat was a feature I was proud of ... until this happened.)

The second bug? On any NAK, the design starts the sequence over. Sure, it flags the restart for software to notice, but ... software never checked (3rd bug?). So I thought the entire thing was working when ... nothing was working.

Competing bugs are rare, but they do happen. Here's a trace showing the first part of one such bug pair when controlling I2C. The trace starts with an interaction with an I2C mux, a TCA9548A -- useful for letting one master control multiple I2C slaves all having the same address

@ATaylorFPGA @OfMikeAndMen Well said by despair.com ...

Most issues are simple, but that would not lead the level of government or taxes we have. One sad thing about aging is realising many people / organisations who focus on a particular challenge e.g. homelessness, drugs, college debt etc have no interest in solving the issue but making a good living from it.

I think one of the greatest lies we have all fallen victim to is that all modern problems require complex solutions. In reality, this is much rarer than one would think.

@AvrajitSarkar4 If the master chooses to de-assert RREADY, that's the master's choice. It's not a bug in the slave's logic. Many masters will legitimately do this, and the slave must be able to deal with it properly.

@zipcpu If arvalid and rready both are asserted by the master the ar handshake will complete and due to the coding style even r channel will also complete but if the master desserts the rready the rvalid would remain high and the slave would get stuck and the bus would get crippled.

Here's a bug of the day for you, this time from an AXI-Lite slave controller written by ChatGPT. See if you can see it.

@curliph Partial address decoding isn't a "bug". It's an optimization. Done properly, the AxADDR width should be restricted to the bare minimum required by the slave. Given that I didn't share the width of AxADDR, you really can't tell if this was intended or not.

@zipcpu gpt 5.6 Sol seems more power for review. But I think try to figure out the bugs caused by AI is not worthy and somthing waste time. This type of error should be covered by formal loop. Writing code with agent is a "harness" work, just providing prompt is not sufficient.

@CosplayFloorRev A transaction is requested by the VALID, accepted by the READY. Dropping the request once it has been accepted is a typical part of the protocol. Consider this article: zipcpu.com/blog/2021/08/2…

@zipcpu Sorry, not that familiar with AXI. I might get the idea now. Is the negation done to prepare for a new read and thus reset the state for the validation of a new response?

@CosplayFloorRev When would you suggest negating RVALID then?

@zipcpu Seems weird to negate S_AXI_RVALID if it and S_AXI_RREADY are true. Might be wrong but that's my observation.

@AvrajitSarkar4 Crippled throughput could still be valid AXI. This example, however, is not even specification compliant.

@zipcpu Crippling throughput. After finishing one transaction it needs to wait for one cycle before asserting arready and rvalid .