Ed Sperling

New adaptive, mesh NoC topologies are enabling chip designers to optimize data movement in complex SoCs and multi-die systems. semiengineering.com/data-boom-puts… #NoCs #chiplets #interconnects #networkonchip #semiEDA #semiconductor

High-speed data movement will be required in future vehicles, probably including optical, but challenges persist. semiengineering.com/auto-ethernet-… #AutomotiveEthernet #Ethernet #automotive

Step-by-step application of AI in EDA. semiengineering.com/how-ai-will-au… #semiEDA #AI #chipdesign @Cadence #AgenticAI #AI #autonomouschipdesign

Latest: US AI framework; GPU smuggling; HBM4; war’s impact on supply chain; GTC; restart of H200; memory prediction; TFLN photonics; test/metrology platforms; NoC verification automation; AI distillation attacks; high-NA EUV..semiengineering.com/chip-industry-… #semiEDA #DRAM #semiconductor

Progress is steady, but fundamental questions remain. semiengineering.com/2d-semiconduct… #2D #semiconductor #TMDs #DFETs

Why new LPDDR releases make them the memories of choice for many applications. With memory expert Steve Woo, Rambus fellow and distinguished inventor semiengineering.com/memory-for-ai-… #LPDDR #DRAM #AIDataCenters @rambusinc #inferencing #GDDR

How new equipment and methodologies are improving reliability, yield, and time-to-market for multi-die assemblies. semiengineering.com/tool-and-metho… #semiconductor #advancedpackaging #metrology @cohu_inc @oontoinnovation @yieldWerx #ASE #DataAnalytics #metrology

Architecting solutions for edge AI is not about minimizing cloud solutions or making small extensions of existing MCUs/MPUs. It’s a HW/SW/model co-development problem. semiengineering.com/ai-power-on-th… #EdgeAI #lowpower #semiconductor

Digital Twins: The Cloud’s The Limit semiengineering.com/digital-twins-… Chip industry leverages massive compute resources and AI for virtual sandboxes. #digitaltwins #virtualtwins #multiphysics #AI #semiconductor #DFT #SLM

Latest: Preparing for sub-1nm; Iran war fallout on chips; Embedded World; ramping Japan; foundry rankings; MIPI PHY IP; clocking tech; imec’s new consortium; neuromorphic computing; AI chips; photonics; sensors semiengineering.com/chip-industry-… #semiconductor #neuromorphic #EmbeddedWorld

For reaching farther into another data center, developers are now talking about scale-across. semiengineering.com/scale-up-scale… #scaleup #scaleout #datacenters #Ethernet #scaleacross

New techniques are needed to keep pace with ever-shrinking features and tolerances. semiengineering.com/tool-matching-… #semiconductor

Yield loss is increasingly molecular in origin and invisible to conventional inspection. semiengineering.com/detecting-chem… #semiconductor #yield #chemicalvariability #waferdefects

New technical papers recently added to Semiconductor Engineering’s library semiengineering.com/chip-industry-… #semiconductor #GPU #AIaccelerators #OxideSemiconductors #Edge #RPU #AIhardware #IMC

Exponential increases in data and a mix of performance requirements are driving a top-to-bottom rethinking of what works best where. semiengineering.com/new-automotive… #automotive #ADAS #LPDDR6 #SDVs

Latest: AI integrity attacks; US weighs more AI chip authority; bid to buy Rohm; new chips at MWC; optical interconnect deals; CPO funding; 18A; domain-scoped agentic AI; HBM4; automotive chips; BYD’s 9-minute EV charge ... semiengineering.com/chip-industry-… #semiconductor #AIsecurity #HBM

OEMs are driving faster design cycles and enhanced security amid evolving vehicle architectures and compliance requirements. semiengineering.com/auto-security-… #automotive #automotivesecurity

Engineering specialization is still required, but time to market will shrink for FPGAs and DSPs. semiengineering.com/ai-starting-to… #FPGAs #DSPs #programmablelogic #AI #eFPGA #compilers @AlteraFPGA_ @AlphaDesignAI @AMD @Cadence @Synopsys @Infineon @Siemens @arteris_noc @bayasystems