Om Gupta

Ive built a multi warp SIMT gpu core which supports Branch Divergence(IPDOM STACK) in SystemVerilog

@spr4bhu @Vicharak_In crazy work!

The PicoRV32 example on the Shrike board by @Vicharak_In is now runtime-programmable. Drop in any 32 RV32I instructions over SPI and run them on the fly. No re-synthesis, No new bitstream.

resources: Harris and Harris digital design textbook Programming massively parallel processors by Hwu and Kirk General-Purpose Graphics Processor Architectures by Aamodt, Fung, and Rogers Onur Mutlu 's digital design lectures on vector processors

Ive built a multi warp SIMT gpu core which supports Branch Divergence(IPDOM STACK) in SystemVerilog

heres the github link: github.com/Omie2806/gpu refer the readme to understand the architecture properly

So, this gpu overall supports basic arithmetic instructions and the mentioned branch instructions.

Whenever a warp stalls, the warp_scheduler switches to the next ready warp.(stalling happens on load/store instructions)

I've added BEQ, BLT and JUMP instructions(ipdom pc is encoded in the instruction itself)

It supports 8 stack registers per warp and the not taken branch in always executed first