RISC-V International

Memory safety is one of the biggest challenges in modern systems software. Want to see how CHERI approaches it? The recording of “Hands-on Introduction to CHERI” is now available. In this workshop, Alfredo Mazzinghi (CHERI Alliance) and Marno van der Maas (lowRISC) introduce the fundamentals of capability-based security and guide you through hands-on exercises using CHERI and CHERIoT. You'll explore: • The CHERI hardware capability model • Memory safety and pointer integrity • Practical CHERI C/C++ examples • CHERIoT and secure embedded systems Download the workshop materials, follow the setup instructions, and work through the exercises alongside the recording at your own pace. 🎥 Watch the recording: hubs.la/Q04pQh3V0 More recordings from the #RISCVDeveloperWorkshops in Bologna are on the way, so stay tuned.

Ready to build experience that actually matters? Explore the current paid mentorship opportunities with RISC-V Member Organizations. As a mentee, you'll gain exposure, build experience through a focused, real-world project, grow your network, and get paid to learn! 📅 Program timeline: September 1 to November 30, 2026 📝 Apply by: August 5, 2026 See available mentorships: hubs.la/Q04nT2H00 #RISCVmentorship #LearnRISCV

Missed the #RISCVDeveloperWorkshops in Bologna?  Join Jordan Carlin and David Harris for the RISC-V Architectural Certification Tests Early Adoption Workshop. Learn about the certification tests, the early adoption program, and how you can get involved. 🎥 Watch the recording: hubs.la/Q04nT0L20 More RISC-V Developer Workshop recordings will be released in the coming weeks, so keep an eye out for the next sessions.

The #RISCVDeveloperWorkshops weren't meant to be recorded, but we changed the plan! The first recordings are here. 🎉😉 Learn how to bring up ExecuTorch on a RISC-V microcontroller with Jeremy Bennett. This hands-on session walks through the process and provides practical guidance to help you get started with on-device AI on RISC-V. 🎥 Watch the recording: hubs.la/Q04nTpX80 (hubs.la/Q04nTpX80) More recordings from the #RISCVDeveloperWorkshops in Bologna are on the way, so stay tuned.

Smart glasses that can interpret eye movements in real time, without relying on the cloud. Powered by the GAP9 RISC-V multicore processor, GAPses processes electrooculography (EOG) signals directly on the device, classifying eye movements in real time. The result is a privacy-preserving, energy-efficient wearable platform for always-on biosignal inference. Presented at RISC-V Summit Europe, this #RISCVfeaturedwork demonstrates how #RISCV enables sensing, machine learning inference, and decision-making at the edge, opening new possibilities for wearable neural interfaces. Explore the project on our blog and discover how edge AI is helping bring real-time biosignal processing to wearable devices. - hubs.la/Q04nJRsY0

🇨🇳 RISC-V Summit China is back! From October 18-20, the global RISC-V community will gather at the Shenzhen Convention & Exhibition Center for one of the largest RISC-V ecosystem events of the year. Join industry leaders, developers, researchers, and innovators from around the world for three days of technical sessions, ecosystem updates, networking, and the latest breakthroughs driving the future of open computing. Save the date and stay tuned for registration, speaker announcements, and more. #RISCV #RISCVSummitChina #RISCVEverywhere

👉 For the first time in Italy, the @risc_v Summit Europe brought international experts to Bologna to discuss this leading standard for processors. 💻 The event offered great networking opportunities, including last night’s dinner at Palazzo Re Enzo. 🔗 bwelcome.it/mice-events

🌳 What if forests could report their own conditions in real time? This morning’s “Internet of Trees” talk explored a vision of low-power, RISC-V-based sensors embedded in forest canopies to capture environmental data directly at the source. More than data collection, it’s about building long-lasting, open systems to better understand and protect ecosystems. #RISCVEverywhere #RISCV #RISCVSummitEurope

Coffee in hand? Before you head back to sessions, take a walk through the poster area. With 71 new posters every day, there's no shortage of innovation and inspiration. What's the most interesting thing you've found so far? 👀 #RISCVSummitEurope #RISCV

Day 2 is underway, and @kasanovic’s State of the Union keynote delivered a clear message: 💪 The state of the union is strong. RISC-V is firmly established in embedded, becoming the standard base for new AI accelerators, and moving closer to widespread adoption in application processors. With server-class RVA23 silicon arriving in 2026 and the Server Platform Specification now ratified, the foundation for the next phase of growth is taking shape. The momentum continues in Bologna 🚀 #RISCVSummitEurope #RISCVEverywhere

What a way to kick off #RISCVSummitEurope 🚀 Day 1 featured discussions on AI and accelerated computing, software ecosystem development, security, embedded systems, automotive applications, and the innovations helping drive RISC-V adoption across industries. Now it's time to keep the conversations going. The Welcome Networking Reception, sponsored by @DeepComputingio, has officially begun! 🍹✨ Whether you're reconnecting with familiar faces or meeting someone for the first time, this is where some of the best Summit conversations happen. See you tomorrow for Day 2.

“RISC-V is happening right now.” 🚀 Fresh off his opening keynote at RISC-V Summit Europe 2026, CEO Andrea Gallo joins James De Vile to unpack the momentum behind the ecosystem — from major investment in SiFive and Axelera AI, to the Server Platform Spec 1.0, RVA23 silicon, and the first RVA23 laptop. A fast-moving conversation on why 2026 is already a defining year for RISC-V. 🎥 Watch the interview > youtu.be/pJIiAnS8N7E?si…

Afternoon sessions = unlocked 🔓 Take a look at what's coming up next 👇 Between sessions, be sure to wander over to the Developer Zone, explore the Expo Hall, walk through the poster room, and catch the latest demos in the Demo Theatre. (Trust us, you won't want to spend your entire break checking email.) #RISCVSummitEurope #RISCVEverywhere

"Work upstream early." A simple message from today's keynote by Greg Kroah-Hartman: save time, save money, and avoid costly rework by engaging upstream from the start. Want to learn more? Check out what Greg had to say in our blog from earlier this year! ➡️ riscv.org/blog/risc-v-up… #RISCVSummitEurope #RISCVEverywhere

☕️ Morning break = Expo Hall time. The Expo Hall is now open at #RISCVSummitEurope. Meet exhibitors, discover new technologies, and see the latest RISC-V innovations. And don't miss the Developer Zone on your way 👀 #RISCV

RISC-V International CEO, Andrea Gallo kicks off the day with an update full of announcements: - RISC-V market penetration set to go from 2.5% to 33.7% in just 10 years - Microsoft and Tenstorrent upgrade to premier board members of RISC-V international - Server platform specification 1.0: Industry Standard boot architecture and runtime services, portable system software can rely on the platform, interoperability between conforming servers and portable system software, built on top of RVA23 #RISCV #RISCVSummitEurope #RISCVEverywhere

🎉 Summit Day 1 is here! The keynote room is set, attendees are filing in, and the energy is building as we get ready to kick off RISC-V Summit Europe 2026. Take a look below for this morning's schedule and follow along throughout the day for highlights, insights, and announcements from Bologna. #RISCVSummitEurope #RISCV #RISCVEverywhere

I spy @pulp_platform 👀

We’re in Bologna 🇮🇹 Member Day + Developer Workshops kick off today, and the main conference starts tomorrow at RISC-V Summit Europe. Still thinking of joining? You can register on-site at the door (credit card only). Let’s go 🔥 #RISCVSummitEurope #RISCV