RISC-V International

Newest Featured Work – See what others are building on RISC-V Docker on RISC-V is moving at a different pace now. With community-maintained packages, Docker v29 is available on RISC-V64 within days of release, not months. Fully automated pipelines compile natively on RISC-V hardware and deliver the full stack as installable .deb and .rpm packages: Engine, CLI, Compose, and Buildx. No workarounds. No missing features. Just parity. This is what it looks like when a community gets ahead of the ecosystem. Explore how it all came together and what it unlocks for developers working on RISC-V. hubs.la/Q04dSgmB0

Hardware or Software? Why not both. Join us in Bologna on 8 June for the RISC-V Developer Workshops, happening the day before #RISCVSummitEurope. We’re bringing hands-on, expert-led sessions across both tracks, so you can build, test, and learn by doing, not just listening. €30 for a full day. Limited seats available. Check out the agenda and save your spot 👉 hubs.la/Q04cYgkm0 #RISCV #DeveloperWorkshops #Hardware #Software #RISCVDeveloperWorkshops

🚨 We’re live at Microelectronics today and tomorrow. If you’re attending, make your way to Booth 430 and meet the team! 🎤 Don’t miss Tom Gall, our VP of Technology, speaking on RISC-V and the Future of Open Architectures. A must-attend session for anyone interested in what’s next for semiconductors, innovation, and open collaboration. #RISCV #RISCVEverywhere

A full day to build, test, and learn RISC-V. Join us on 8 June in Bologna for the RISC-V Developer Workshops, just before #RISCVSummitEurope. We’re running hands-on sessions across both #software and #hardware tracks, led by experts from across the #RISCV ecosystem. Just practical work, and things you can apply right away. €30 for the full day. Limited seats available. Save yours now! Register here 👉 hubs.la/Q04d09NX0

💡 Predict before you implement. Thales built a precise performance model for the CVA6 RISC-V core to evaluate changes before touching RTL. The model achieved COREMARK performance results that were within 0.8% of the RTL, uncovering performance bottlenecks and informing the design of a dual-issue CVA6 core. Outcome? A 40% performance boost with just +7% power and +11% area. This shows how modeling can transform open hardware development. Explore the project here: hubs.la/Q04c5j7G0

Curious about what you can actually build on RISC-V? This is where things get hands-on. Join us for a day of hands-on workshops designed for developers who want more than slides. You’ll experiment with tools, test what works today, and see how #hardware and #software can be co-designed. We’re going all in on practical learning, direct application, and the chance to start building right away alongside experts and other developers and engineers. Check out the #RISCVDeveloperWorkshops’s agenda, and join us! 😎 hubs.la/Q04c5lLL0 ________________________________________________ 🎟️ €30 pass | Open to all 📅 Monday 8 June 2026 📍 Palazzo dei Congressi, Bologna, Italy #developers #RISCV #Bologna #RISCVSummitEurope

Looking for a way to gain real experience this summer? RISC-V Member Organizations are offering paid mentorships where you can work on real-world projects, get exposure to industry teams, and learn by doing. And yes, you get paid while learning! 📅 Summer Program: June 1 to August 31, 2026 📝 Apply by: May 17, 2026 Take a look at the current opportunities and find the one that fits you: hubs.la/Q04c5ns30 #RISCVmentorship #LearnRISCV #RISCV #jobopenings

👩‍💻 CALLING ALL #DEVELOPERS 👨‍💻 in #Italy and around the world! Ready to go beyond theory and start building? Join hands-on #RISCV workshops led by industry experts across #hardware and #software tracks. Whether you’re deep into RISC-V or just getting started, roll up your sleeves and get practical with the open standard everyone’s talking about. 🎟️ €30 pass | Open to all 📅 Monday 8 June 2026 📍 Palazzo dei Congressi, Bologna, Italy 👉 Save your spot. Space is limited: hubs.la/Q049bYgH0 #RISCVeverywhere #RISCV #OpenStandard #ISA #RISCVDeveloperWorkshops

🔍 How do you accelerate real hardware innovation? Thales shows the power of performance modeling with the CVA6 RISC-V processor. Using a cycle-accurate Python model, they identified and tested performance improvements before RTL implementation, guiding the creation of a dual-issue CVA6 core. The result: +40% CoreMark/MHz with only modest increases in power and area. This is a clear example of modeling driving smarter hardware design. 👉Check out the short walkthrough video and the project: hubs.la/Q0482g6d0

The #RISCVDeveloperWorkshops are coming to RISC-V Summit Europe in Bologna. 🇮🇹 Spend the day building on RISC-V with hands-on workshops led by industry experts across hardware and software tracks. Designed for #developers who want to move beyond theory and into action — all for just €30. (Space is limited. Secure your spot.) Learn more: hubs.ly/Q049br760 📅 Monday 8 June 2026 📍 Palazzo dei Congressi, Bologna, Italy

The race has begun 🏁 Amazing to see that some of you have reached bronze and silver, and more are joining every day. Participants in the #RISCVCommunityChallenge with HaDes-V are advancing through the first milestones as they build their own RISC-V microcontrollers. The challenge is officially underway, but you can still join. (Deadline to register: April 3) Jump in, learn, and build at your own pace: hubs.la/Q047ql7G0

The momentum behind @risc_v continues to accelerate at the #Xuantie Ecosystem Conference in Shanghai. Charles Janac, our President and CEO, presented “Optimizing Data Movement Across XuanTie Systems” there. We have more events planned throughout the year - stay tuned 👋🏻

Announcing our first keynote speaker, Greg Kroah-Hartman 🎤 We’re excited to welcome Greg Kroah-Hartman to the RISC-V Summit Europe stage. As the maintainer of the Linux stable kernel, Greg plays a critical role in ensuring the reliability and long-term support of Linux across a wide range of systems. In addition to his keynote, Greg will also be joining us at Members Day to connect with the broader RISC-V ecosystem. Stay tuned for more speaker announcements. Learn more about the event > riscv-europe.org/summit/2026/ #RISCVSummitEurope #RISCV #RISCVEverywhere

How do we make RISC-V Vector Extensions more accessible for scientific applications? This featured project for March introduces a new RVV backend for the RAJA framework, enabling portable, vectorized performance across heterogeneous systems. It is a big step toward making RVV practical for real-world scientific and HPC workloads. If you are into performance, portability, and open computing, this one is for you. 👉hubs.la/Q043jJGH0

Ever had someone spend just a few minutes helping you and it completely changed your path? That’s exactly what happened to our Community Director, Megan. She went from tinkering with headgear to speaking on stage, all because someone took a moment to mentor her. Since the RISC-V Mentorship Program launched in 2021, we have grown from 6 mentees in the first year to 49 mentees in 2025, showing the significant impact mentorship can have. We still need more mentors to create opportunities for the hundreds of applicants eager to learn and grow. Summer 2026 Mentorship proposals are open through March 30. Let’s pay it forward and help the next generation of RISC-V innovators thrive! Apply now to become a mentor: hubs.la/Q046lyJr0

If you enjoy #Hackathons, you'll love the #RISCVCommunityChallenge. The challenge with HaDes-V kicked off last week. Learn to design and build your own pipelined 32-bit RISC-V microcontroller. Watch the recording and get all the details here: hubs.la/Q045BDl70 Register by April 3 and jump right into the challenge with everyone else. 🙌🤠

This week at embedded world 2026, join two ecosystem panels on how RISC-V is shaping the future of embedded innovation. Hear insights from Siemens, Andes, Semidynamics, SiFive, Akeana, Nuclei, Synopsys, and DAMO Academy. 📍 Hall 5 Exhibitor Forum ⏰ Tue Mar 10, 10AM | Wed Mar 11, 3PM #ew26 #embeddedworld #RISCV #RISCVEverywhere

Last chance to submit. The Call for Proposals for RISC-V Summit Europe 2026 closes March 9. We’re looking for strong technical talks and papers covering real-world RISC-V work, from AI and platform engineering to security, research, and upstream contributions. Submit: riscv-europe.org/summit/2026/ca… #RISCV

Collaborate. Guide. Build together. Work with motivated mentees and make real progress on your project this summer. RISC-V International handles stipends and onboarding, so you can focus on mentoring and building. 📅 Summer session: June 1 – Aug 31, 2026 📝 Submit your proposal by March 30, 2026: hubs.la/Q045wkzv0

New #RISCVFeaturedWork for March: A solid resource for anyone working on #HPC, scientific computing, compilers, or RISC-V vector extensions. 👇 Support RAJA and Scientific Applications on RVV Architectures showcases how RVV can be integrated into the RAJA performance-portability framework to unlock vector acceleration for scientific workloads. By adding a new RVV backend to RAJA’s vectorization API, this work makes it easier for developers to write portable, high-performance code that runs efficiently across heterogeneous systems, including RISC-V vector platforms. 🤓Check out the short walkthrough video and the project: hubs.la/Q043jG1F0