katatsumuri

Luckily AMD has kept Xilinx mostly intact. I hope they continue to do so. I just wish Xilinx tools were as good as pre-Intel versions of Quartus.

If Intel spent a fraction of the effort they put into rebranding PDFs (don't get me started on changing the binary content of a reference PDF without revision notes) into keeping old documentation, this wouldn't be a problem.

@intel Why have you let the old altera.com links rot? FPGAs have long product cycles, and even obsolete parts need support. The first step to re-implementing an old design on new hardware is reproducing the design on the original hardware. altera.com/products/board…

@enjoy_digital @tnt What goes wrong with the connector? I have a VCU1525 and would prefer not to break it...

@tnt Yes, does not work unfortunately. The board is a desk decoration for quite some months now and I'm now preventing this on others by using PCIe power and this :):

8 months old and already LUTs multi-millionnaire! Never to young to start playing with FPGAs, even if the VU9P is used here as a 💵💵💵 mirror 😄🥰. Precision: Dad accidentally broke the board thanks to Xilinx's very clever connector...

@RaptorCompSys I could measure on wiki.raptorcs.com/w/images/4/44/… and then work backward from known ATX dimensions. But this is unlikely to meet the tolerances required by Samtec connectors. Ideally, the PCB layout + BOM would provide what I need, but I can see why you might not want to share that.

@RaptorCompSys I'm looking for precise connector / header positions. I'd like to design a board that connects to both J10111 (Flexver) and J3200 (FSI + "CP0 Characterization Connector"). This would give my arctic tern access to LPC_BMC_LAD*_SECURE. Unfortunately the geometry is rather complex.

@RaptorCompSys Can you make 3d models of the Talos II and Blackbird available? The mechanical drawings included on the wiki are helpful. Unfortunately they're difficult to use when modeling how the boards might fit in an enclosure or designing a companion PCB.

@RaptorCompSys Any format is fine!

@RoboMuu Possibly. What format are you looking for?

@RaptorCompSys arstechnica.com/information-te…

@RaptorEng @RaptorCompSys I was reading about the exciting Kestrel Collaboration when I noticed gitlab.raptorengineering.com/explore has a problem with spam projects that started around a month ago.

@RaptorEng Is it possible to switch PEC2 (CPU 2, Slot 3) into x8x8 bifurcated mode on the Talos II? The Power9 documentation suggests that this is possible for PEC1 & PEC2. I assume the setting needs to be changed sometime early in the boot process?

@furan This is a big jump from your usual Stratix or APEX 20K + PCI!

Staring at the options for the 10-series PCIe hard IP in Quartus Pro.

@Betavulgaris6 I have fond memories of using MGC on Solaris from this era. I haven't been able to track down a copy yet. If I'm remembering correctly, MGC had very nice mouse gesture support.

Finally got it running!

Finally, the internals of Viewlogic Powerview/Workview Office are being revealed. With symbol information, of course! From @mentor_graphics Board Station 2004 for Linux.

@Betavulgaris6 I've considered making a carrier board for the FLEX 10KE. ClockBoost is nice, but the true killer feature for me is dual port EABs. I do miss the 84-Pin PLCC package option.

@RoboMuu FLEX 10K Series are true 5V (core voltage), while the inputs of FLEX 10KA/KE Series are 5V tolerant.

I made MC68010 and AS6C4008 breakout boards for the Altera UP2!

Here's the pinout for SPI FLASH + FIRMWARE header

The PSDB_FIBER mezzanine card has a SFP cage and a camera link connector. There's also a second unpopulated SFP cage footprint. As far as I can tell, the SFP should connect to a remote SFP-to-camera-link module.

A new ebay find arrived this week! GiDEL PROCe-III80-B with a mysterious PSDB_FIBER mezzanine board.