SiFive

The energy was electric at the TSMC 2026 Taiwan Technology Symposium, where the future of AI was on full display and our SiFive experts were on hand to showcase our latest products and connect with customers. Huge thanks to TSMC for the opportunity to join this event! #TSMC #SiFive #RISCV #Semiconductors #AI #Innovation

SiFive is excited to be a part of the TSMC 2026 Taiwan Technology Symposium on May 14. Stop by and meet with our experts at the Sheraton Hsinchu Hotel to talk all things SiFive and explore our RISC-V solutions. See you in Taiwan! 🇹🇼 #TSMC #SiFive #Hsinchu #TechSymposium

SiFive and HighTec EDV-Systeme are collaborating to streamline the development of safe and secure software for automotive and industrial applications. na2.hubs.ly/H05n1cX0

RISC-V is no longer just for low-power embedded tasks, it's moving into high-performance territory traditionally dominated by proprietary ISAs. Join the Futurum webinar on May 27 at 8:00 AM PST to see how SiFive is redefining compute with out-of-order RISC-V cores that rival best in-class from legacy architectures. We’ll break down SiFive's latest performance products, the importance of compatibility with the RVA23 profile, and how to build faster, more scalable systems on a open standard. Register here: na2.hubs.ly/H05jcg30 #RISCV #Semiconductors #TechWebinar #SiFive #HighPerformanceCompute #Innovation

Inside SiFive | Episode 1: RISC-V and the Automotive Market The automotive industry is at a turning point. As ADAS and zonal designs redefine the vehicle, the shift toward the RISC-V open standard architecture is accelerating. Join us for the first episode of the “Inside SiFive” podcast series. In this wide ranging and informative conversation, SiFive experts share key insights about the state of RISC-V within the automotive industry and how SiFive is in the driver's seat to meet customer needs for the next generation of vehicles. Watch the pilot episode here: na2.hubs.ly/H05jczp0 Learn how SiFive™ Automotive solutions provide the flexibility and performance required for the road ahead: na2.hubs.ly/H05jcg20 #RISCV #SiFive #AutomotiveTech #ADAS #ZonalArchitecture #ProcessorIP #OpenStandard

May the 4th Gen be with you! The SiFive Essential™ 4th Gen processor IP is the ideal solution for a vast galaxy of embedded and real-time control applications. Whether you are designing for droids, speeders, or in-cockpit instrument clusters running RTOS or rich Linux environments, this is the IP you are looking for… Throw that legacy ISA into the trash compactor and join us in the RISC-V revolution. Discover how open standard designs can accelerate your next mission. Contact us to learn how! #SiFive #MayTheFourthBeWithYou #Semiconductors #TechTransformation #RISCV #StarWarsDay #EmbeddedSystems

Catch us at Booth #520 at the TSMC 2026 Technology Symposium. Stop by right now to chat with our experts and see our latest architectures in action. Learn how our latest RISC-V architectures accelerate performance for AI applications from Embedded Edge to the Data Center. Discover why SiFive is the RISC-V gold standard. #SiFive #TSMC2026 #RISCV #Semiconductors #AI #Innovation #Compute #SantaClara

Join SiFive at the TSMC 2026 North America Technology Symposium to see how we are reshaping the global compute landscape. As the trusted partner for RISC-V IP innovation, we are leading the revolution by empowering chip designers with high-performance and power-efficient processor IP. Stop by Booth #520 at the Santa Clara Convention Center on April 22nd to learn how our latest RISC-V architectures accelerate performance for AI applications from Embedded Edge to the Data Center. Discover why SiFive is the RISC-V gold standard. Date: April 22, 2026 Location: Santa Clara Convention Center, Santa Clara, CA Booth: #520 #RISCV #DataCenter #AI #SiFive #TSMC2026 #Semiconductors #TSMC

Thank you @Nasdaq for celebrating SiFive's funding milestone. Exciting to see our logo in #TimeSquare. Maybe one day we will be there to ring the bell!  #SiFive #RISCVMomentum #IPOBound #Nasdaq #RISCV #AgenticAI

It was cool to see our logo inside the exchange. Thank you @NYSE for the recognition of our latest funding milestone and for giving Wall Street a preview at what could be down the road… #SiFive #RISCVMomentum #IPOBound #NYSE #RISCV #AgenticAI

BIG NEWS: SiFive has successfully closed an oversubscribed Series G financing round of $400 Million, bringing our valuation to $3.65 Billion. Led by Atreides Management, with participation from A-list investors including NVIDIA, this investment is a major vote of confidence, with funds targeted specifically to accelerate SiFive’s high-performance RISC-V data center solutions roadmap to service the outsized demand for Agentic CPUs within the hyperscalers. As CEO Patrick Little notes, "As the industry evolves toward agentic AI, SiFive is doubling down on the data center. Through collaborations with our customers we are uniquely positioned to capture a meaningful portion of the massive agentic AI shift." We are excited to continue pioneering, and to be leading the RISC-V revolution into the next era. Read the Press Release: na2.hubs.ly/H04MT6W0 Read the Blog: na2.hubs.ly/H04MTvc0 #RISCV #AgenticAI #DataCenter #VentureCapital #Semiconductors #SiFive #AIInfrastructure

Join us for a free, 60-minute live webinar to explore why RISC-V IP is moving rapidly into the practical implementation phase. As a leading RISC-V IP vendor, SiFive will be diving into the technical trends and real-world applications shaping the industry today. Title: SiFive – Latest Trends in RISC-V IP: Entering the Practical Implementation Phase Date: April 21, 2026 Time: 10:00 – 11:00 (JST) → SiFive Featured Session (10:00 - 10:30) Cost: Free We’ll be introducing our latest product portfolio and discussing the shift from "Concept" to "Practical Use" at the forefront of RISC-V technology. Whether you are an architect, engineer, or tech leader, this is a deep dive you won't want to miss. 👉 Register here to secure your spot: na2.hubs.ly/H04HrYY0 #SiFive #RISCV #Semiconductors #Webinar #TechTrends #Innovation #JapanTech

Why wait for silicon? 🛡️ @Synopsys collaborates with SiFive to deliver Synopsys VDKs for our diverse range of automotive certified processors. By providing cycle-accurate models within the Synopsys Electronics Digital Twin Platform, we’re helping engineers conquer the complexities of new zonal architectures with real-time precision. Check out how we’re accelerating the future of mobility. na2.hubs.ly/H04Cflx0 #AutomotiveDesign #DigitalTwin #EmbeddedSystems #SiFive

Why the "Zonal Shift" Demands a New Approach for Automotive Compute The modern vehicle is no longer just mechanical; it’s a highly complex electronic system of sensors, wiring and compute. In many cases car manufacturers are having to completely re-engineer their cars from the ground up.  As part of this, automotive architectures are evolving to Zonal controllers to reduce cost, weight, and power. Strict real-time performance, functional safety, and cybersecurity are no longer "nice-to-haves"—they are the baseline. At SiFive, we believe RISC-V is the key to unlocking this next generation of automotive. By leveraging an open-standard ISA, we aren't just improving performance; we are: ✅ Boosting supply chain resilience. ✅ Bringing standards-based RISC-V ISA for safety and compute ✅ Providing customers with a roadmap backed with years of investment The future of automotive is open, with freedom from single-vendor lock in. Discover how SiFive is powering the Zonal revolution: na2.hubs.ly/H04nMGc0 #AutomotiveDesign #RISCV #ZonalArchitecture #Semiconductors #SiFive #FutureOfMobility

Ever wondered how RISC-V stays so efficient while keeping hardware simple? It all comes down to how we handle addressing modes in software rather than hardware. In our latest technical blog, we explore the vital role of Code Models within the RISC-V toolchain and how they empower designers to optimize performance. Key Takeaways: ▪️Simplicity by Design: RISC-V minimizes hardware costs by using only three basic addressing modes: PC-relative, Register-offset, and Absolute. ▪️Software Flexibility: We rely on modern toolchains to optimize addressing, achieving similar code size to complex ISAs with vastly simpler decoding rules. ▪️Medlow vs. Medany: Learn the functional differences between these two primary code models and how they determine where your code can be linked in the address space. ▪️ABI vs. Code Model: We clear up common misconceptions about how code models interact with function interfaces and pointers. By using fusible multi-instruction sequences and linker relaxation, RISC-V offers the power of variable-length addressing without the hardware bloat. Read the full technical breakdown here: na2.hubs.ly/H04lCV_0 #SiFive #RISCV #Semiconductors #ComputerArchitecture #Coding #TechBlog #OpenStandard

Happy Pi Day! 🥧 At SiFive, we believe you should never have to compromise on your architecture. Our mission is to lead the RISC-V revolution by empowering you with high-performance, customizable, and open-standard processor IP. Why settle for a "pre-baked" solution? With SiFive, you truly can have your pi and eat it too: • Customization Without Compromise: Use our Core Designer tool to tailor your IP to your exact workload. You get the specific performance you need without the overhead of unused features. • The Gold Standard of RISC-V: Our SiFive Intelligence™ family leverages the RISC-V Vector (RVV) extension to handle massive mathematical workloads and AI models with unmatched efficiency. • Limitless Potential: From Automotive to Data Centers, we provide the flexibility to avoid vendor lock-in and build silicon that differentiates your product in the global compute landscape. Stop choosing between flexibility and performance. Unlock your potential with the freedom to innovate on the open standard. #PiDay #RISCV #SiFive #Innovation #CustomSilicon #AI

Hello, SNUG Silicon Valley! The SiFive team is live at the Santa Clara Convention Center for Synopsys Converge 2026. If you're attending, come find us tomorrow for a deep dive into the latest RISC-V innovations. Our experts are on-site and ready to discuss how we’re shaping the future of high-performance compute together. 📍 Where: Santa Clara Convention Center 📅 When: We’re here through tomorrow, March 12th! Stop by, say hello, and let’s talk about what’s next for semiconductor design. See you there! #SiFive #Synopsys #Converge2026 #RISCV #Semiconductor #SantaClara

A huge thank you to everyone who visited the SiFive booth at the University of Tokyo! It was a great day of technical discussions at the Hongo Campus. We enjoyed sharing how SiFive is leading the RISC-V revolution in Japan and beyond. Our team was proud to showcase: - Intelligence Products: IP specifically designed to accelerate AI and/or pair with customers custom accelerators. - Out-of-Order CPU IP: High-performance designs for applications processing. - Automotive Solutions: FuSa-certified products for safe, software-defined vehicles. If we missed you or you’d like to dive deeper into how our open-standard IP can unlock new design freedom for your next SoC, let’s keep the conversation going! 👉 Connect with us here: na2.hubs.ly/H04cfV40 Arigato gozaimasu, and we look forward to seeing you again soon! #RISCV #RISCVDayTokyo #SiFive #Semiconductors #AI #Innovation #JapanTech #UniversityOfTokyo

We’re in New Orleans and the energy is incredible! If you’re at GOMACTech, there is still plenty of time to connect. SiFive will be at Booth #133 through Thursday, March 12th. Stop by to see our latest Intelligence products and discuss how we’re bringing secure, scalable RISC-V to the next generation of Aerospace and Defense systems. See you in the Big Easy! #GOMACTech #SiFive #RISCV #DefenseTech #NewOrleans

We are excited to share our latest case study featuring Upbeat Technology, who selected SiFive Essential™ E2 and E3 RISC-V CPU IP to power their next-generation edge AI MCUs. By combining efficient 32-bit SiFive cores with their proprietary near-threshold design, UpbeatTech has achieved record-setting efficiency: 1. 16.8 μW/MHz/DMIPS operating at voltages as low as 0.4 V. 2. ~40% lower power consumption than equivalent ARM-based devices. 3. Stable, always-on operation for voice, vibration, and touch sensing via advanced Error Detection and Correction (EDAC). From AI-enabled drones to healthcare wearables, this partnership is redefining what’s possible for intelligent, battery-powered edge devices. 👉 Download the full case study by clicking the link: na2.hubs.ly/H047Zxv0 #SiFive #RISCV #EdgeAI #Innovation #Semiconductors #UpbeatTech #EnergyEfficiency