UCIexpress

#UCIeConsortium will be at #ChipletSummit this Feb 17-19. #UCIe Chairman, Dr. Debendra Das Sharma (@intel) will give a keynote about the open chiplet ecosystem, so stop by booth #211 to chat with UCIe experts. Use code CS26UCIE for $100 off registration: bit.ly/4kcrhNq

#ChipletSummit is only a month away in Santa Clara from Feb 17-19, 2026! Stop by the #UCIeConsortium booth #211 to chat with #UCIe experts and learn about our role in a connected chiplet ecosystem. Learn more about this year’s event: bit.ly/4a0GHRU

#UCIeConsortium is returning as a sponsor at the upcoming 2026 #ChipletSummit in Santa Clara from Feb 17-19, 2026! Stop by our booth #211 to chat with #UCIe experts and see how our membership is already implementing UCIe technology. View the agenda: bit.ly/4a0GHRU

In our latest blog “UCIe Consortium's 2025 Year in Review”, we extend a special thank you to our members whose contributions to #UCIe specification development and ecosystem advancement made 2025 another successful year: bit.ly/4jmC1bP

#UCIeConsortium is a proud sponsor and exhibitor at the upcoming 2026 #ChipletSummit in Santa Clara from Feb 17-19, 2026! Stop by our booth in booth #211 to chat with #UCIe experts and discover our role in the evolving chiplet ecosystem. Learn more: bit.ly/4a0GHRU

In our blog “Why Electrical Design Matters in #Chiplet Architectures – Part Two: UCIe Latency and Security,” by @Cadence and @Synopsys, we explore how the #UCIe Standard addresses latency and security challenges. Read the blog: bit.ly/46wezUw

In our latest #UCIeConsortium blog, hear #UCIe member companies @alphawavesemi, @Siemens, @Synopsys, @Cadence, and @AyarLabs recap their latest webinar - and dive deeper into UCIe enabling cross-company innovation. Read the blog: bit.ly/4rmCaPY

Don’t forget to stop by the #UCIeConsortium Kiosk in the Open Standards Pavilion at Booth # 211 at @Supercomputing this week! Learn more about this week’s event: bit.ly/4mFo2O0

Want to learn more about what the #UCIeConsortium will be up to next week at @Supercomputing? Check out our blog highlighting how you can learn more about the latest #UCIe 3.0 specification from onsite experts at Booth #211 and more: bit.ly/3KYcmcj

Missed last week’s #UCIeConsortium webinar? The full recording of “The Growing #Chiplet Ecosystem: Collaboration, Innovation, and the Next Wave of UCIe Adoption” panel is now available on the #UCIe Consortium website: bit.ly/4qFz9tH

Don’t miss this week’s #UCIeConsortium webinar, “The Growing #Chiplet Ecosystem: Collaboration, Innovation, and the Next Wave of #UCIe Adoption” on Thursday, Oct. 30, 2025, at 8:00 a.m. PT / 11:00 a.m. PT. Register for this week’s webinar: bit.ly/3WmIHvO

Make sure to tune in to the upcoming #UCIeConsortium webinar, “The Growing #Chiplet Ecosystem: Collaboration, Innovation, and the Next Wave of #UCIe Adoption” on Thursday, Oct. 30, 2025, at 8:00 a.m. PT / 11:00 a.m. PT. Register for next week’s webinar: bit.ly/478kBcY

Join us for the upcoming #UCIeConsortium webinar, “The Growing #Chiplet Ecosystem: Collaboration, Innovation, and the Next Wave of #UCIe Adoption” on Thursday, October 30, 2025, at 8:00 a.m. PT / 11:00 a.m. PT. Don’t miss your chance to attend our webinar: bit.ly/478kBcY

Planning your @Supercomputing Series visit? Be sure to include a stop to the UCIe Consortium Kiosk in the Open Standards Pavilion at Booth # 211! Consortium representatives will be available to discuss implementations of #UCIe technology. Learn more: bit.ly/4mFo2O0

If you’re attending the @Supercomputing event next month, stop by the #UCIeConsortium Kiosk in the Open Standards Pavilion at Booth # 211. Consortium representatives will be available to discuss implementations of #UCIe technology. Learn more: bit.ly/4mFo2O0

Our latest #Chiplet 101 blog dives into why electrical design matters for latency, synchronization & security in multi-die systems. As the open standard, #UCIe provides the foundation for high-performance, secure, and scalable chiplet integration: bit.ly/46wezUw

Missed last week’s #UCIeConsortium webinar “The #UCIe 3.0 Specification: Doubling Bandwidth, New Use Cases, and Enhanced Manageability for Scalable SiP Architectures”? No worries - the recording is now live on our YouTube channel! Watch the recording: bit.ly/48tChC8

#ITCTestWeek is next week! Be sure to join the session “#UCIe 3.0 Based Multi- #Chiplets Design & Test” presented by @Intel and @Synopsys on Monday, September 22 from 1:00 - 4:30 p.m. PDT in San Diego. View the full event program: bit.ly/3VuVU56

Don’t miss tomorrow’s #UCIeConsortium webinar “The #UCIe 3.0 Specification: Doubling Bandwidth, New Use Cases, and Enhanced Manageability for Scalable SiP Architectures” on September 18, 2025, at 9:00 a.m. PT. Be a part of tomorrow’s audience: bit.ly/4mSdcom

Our next #UCIeConsortium webinar is only a week away! Don’t miss your chance to register for “The #UCIe 3.0 Specification: Doubling Bandwidth, New Use Cases, and Enhanced Manageability for Scalable SiP Architectures” on Sep. 18, at 9:00 a.m: bit.ly/4mSdcom