Prashant Bagri

@Divyansh91565 Too lazy to teach students how to read a datasheet.

HOW TF IS SOMEONE SUPPOSED TO MEMORIZE EVERY SINGLE PIN AND DRAW THE EXACT SAME DIAGRAM IN THE EXAM , PROF REALLY EXPECTS A PERFECT FIGURE… I'M SO COOKED

Want to play? 😋 A game purely written in verilog. Games are basically state machines, which is a great fit for verilog and FPGA architecture.

@always_ff_rohan This is so cool.

@S2SmeX Just make sure your design validates.

@_prashantbagri I thought I would export it after making it into a proper package. Am I in the correct direction?

I have updated it a bit, but can't understand so many things. can anyone suggest me a good tutorial on it.

@S2SmeX Okay. So you dont have to do that in HLS. Complete you block diag. Crate hdl wrapper -> generate output products -> generate bit stream -> export hardware with Bitstream. Than create a project in vitis ide with with this xsa. And pickup hello world boiler plate. And program.

@_prashantbagri Not in this project. I tried it once, that one is another mess. But somehow I did it. So should I export this ip back to Vitis but shouldn't I add other elements like clock, reset, fifo...

@iyoushetwt Prime example of how boring problems can make money.

iLovePDF is a billion-dollar company???? a BILLION???????? dollars??????????????? for literally.... merging PDFs and converting files to PDF????

@S2SmeX Are you exporting .xsa with Bitstream?

@_prashantbagri Ok can we do that. Cause I was making use of that IP in a block diagram with axi FIFO to trigger inputs to my IP and generating hdl out of it. Can you share any resources, any tutorial or any structured videos.

@SsharmaKirti This is seriously what climate change looks like. Its raining in delhi for last 2 days like its monsoon. And I have never seen it rain here at this time of the year and I have lived here my whole life.

Who hurt you Bangalore? Why you becoming so hot?!!

@S2SmeX From what I can see you have successfully imported IP, and made the block diagram too. So what's the problem? Export Bitstream, and use Vitis ide to program FPGA.

@_prashantbagri Actually I got frustrated, I made this simple matrix multiplier in Vitis and packaged it as IP. Now trying to use it via vivado in order to test on FPGA. I really need a tutorial or guidance, cause currently it's just me & chatgpt.

Sometimes I just think, what if I leave everything. Go home. Start working on my startup, build random stuff. And just get paid.

A guy asked me what's computing in neuromophic computing. Boi. I need to go deep.

@gargipalaskar That's how you know a civilization is going downhill.

it’s more socially acceptable to be on your phone than to read a book at the workplace

@N_and_ni The day I start my company i will keep these nap room at any cost. With blankets, dim lights, and probably slow music playing in background

Don’t you think offices should have a proper nap room?

@kushika_twt Nightmare for front end devs

Startup idea: Curved Laptops.

@benjamincowen This is kind of sentiment will probably keep increasing. Because of AI, people start believing they know something just by asking AI about surface level stuff. Its like saying I read 50 books when you just listened to 5 minute summary. The nuances of subjects are at risk.

Someone could go to school for 4 years and study aerospace engineering, then get a PhD with a dissertation related to orbital mechanics, and some instagram influencer who watched a youtube video will be like "actually that guy is wrong" on a topic related to space travel and people will believe them. I'm not sure how we got here, but I hope we go back to a society where credibility is earned with rigorous training in the associated field, not by a popularity contest.

Godd i hate presentations!!!!!!!

Loving your country should never be synonymous with loving your government.

@vandanasoc28779 Substack. Found some really great long form content there.

Which platform is best to write your content? 1.) Medium 2.) X 3.) Personal Blog 4.) Others