Florian Zaruba

There is an alternate reality where Cray took their vector supercomputers, ditched FP64 calculations, and went with one FP32 pipe and a BF16 tensor core pipe. The same instruction set, memory architecture, and vector registers would have made a sweet deep learning machine, in many ways nicer than SIMT CUDA programming on GPUs. A Y-MP class machine like that could have delivered the AlexNet and DQN moments two decades earlier. Even doing everything in FP64 with no architectural changes, a Cray-1 would have been the best machine in the world for neural networks. If @geoffreyhinton had access to one for early research, the case could have been made for the architectural modifications to 10x the performance.

🌟We have had an amazing time at #RISCVSummitEurope so far! Watch #RISCV Ambassador @FlorianWoh's #recap video, highlighting a few of the incredible Summit announcements, sessions, and activities. We can't wait to see everyone for another packed day tomorrow! #RISCVeverywhere

@pulp_platform @suehtamacv Many congratulations @suehtamacv! 🎊

Matheus @suehtamacv just defended his PhD thesis titled "Fighting Back the von Neumann Bottleneck with Small- and Large-Scale Vector Microprocessors" Congratulations🍾🎇!

@mark_mcgookin @pulp_platform @lucasteske Doom for sure! Crysis is the new benchmark 😅 Occamy should be a new target for the unreal engine

@pulp_platform @lucasteske What’s important is… will it run Doom?

In order to put to rest incorrect information that recently appeared on social media and several more prominent websites, we have published a summary of our project Occamy: pulp-platform.org/occamy/

Cool @AxeleraAI booth at #ew23 looks great. #AI made in Europe And they use #RISCV in some chips Greetings to the #RISCVambassador @be4web

We’re thrilled to share that we have closed our $27million Series A and are ready to launch our AI acceleration platform in early 2023! axelera.ai/european-ai-st… #deeptech #ai #ml #edgeai

@pulp_platform That’s amazing 😍! Looking at the etron homepage I think you are on the path for the smallest Linux-booting RISC-V system. Looking forward to first alive terminal pictures!

It's Friday and we are presenting one of our recently taped out chips, Neo in TSMC65🙂. Neo integrates a Linux-capable CVA6🚀with an enhanced RPC DRAM memory controller for off-chip communication. Thank you Etron for the support: asic.ethz.ch/2022/Neo.html etron.com/innovative-dra…

Wow, congratulations to the entire team, this is such an incredible achievement!

@pulp_platform Looking forward to the floorplan and die-shot on asic.ethz.ch 😍!

Raise your hand if you know tape-out stress. We recently taped out Occamy (more on that soon) and you can see how the expectations and the reports danced around disaster and success for the last few days before the tape-out. No PhD students were harmed during this process😎.

@pulp_platform @mazzergio @ampereproject The new template also fits the NVIDIA colors very well! Superb job 👌

And now something for fans of modern counter-based power models. Here are the slides from Sergio's @mazzergio talk at Samos XXII "A Data-Driven Approach to Lightweight DVFS-Aware Counter-Based Power Modeling for Heterogeneous Platforms". @ampereproject pulp-platform.org//docs/samos202…

Obviously proud!

Hello (ex) @pulp_platform's Ariane/@openhwgroup's CVA6! Thanks to Massimiliano.G's LiteX port, it's possible to regain some freedom: - No longer restricted to Xilinx/Genesys2/MIG. - New peripherals to play with :) - 100% open-source SoC! - ... Try it: litex_sim --cpu-type=cva6

@bilalzafar @LucaBeniniZhFe @pulp_platform @niwist And I would make sure from the beginning that large state holding elements (e.g., predictors) could be implemented as SRAMs, so can cope with at least one cycle latency

@be4web @LucaBeniniZhFe @pulp_platform @niwist Genius! I'm so stealing this for all pipeline diagrams. BTW, I've been curious, what is the most significant change you would make if you were to do Ariane all over again?

Great to see more an more momentum around CVA6, but OMG the picture!! 🤐 @pulp_platform knows what I mean 😜

@bilalzafar @LucaBeniniZhFe @pulp_platform @niwist I would group functional units into fixed latency (alu, fp, etc.) and variable latency (lsu, div). For the fixed latency you can be more lean and clever about your implementation because you know exactly when the result will be produced. While in Ariane everything is handshaked

@bilalzafar @LucaBeniniZhFe @pulp_platform @niwist It’s only purpose is to flush the different stages 😉 but that might be the pain point of @LucaBeniniZhFe 😅

@be4web @LucaBeniniZhFe @pulp_platform @niwist Why is the Controller a toilet seat? :)

@pulp_platform I ❤️ the logo!

We are sharing a couple of our Christmas cookies🍪🎄. These are actually our Minpool dies that just came back from manufacturing. asic.ethz.ch/2021/Minpool.h…. With several ‘min’pools maybe we can make a maxpool, or even a terapool. Now that is an idea.

This is great! That's what I am talking about when I push for open hardware!! Avalanche effect 🚀😎

@_O_N_LANG__ Hey! As of now we manage everything via GitHub (issues). We are happy to help out there! We don’t (yet) have any instant messaging for the public 😕

@be4web Do you guys have a discord or any other chatrooms around the Snitch Processor? I could use some help setting it up to run the first program.