fjullien

Olivier and Julien are in Bochum for HARRIS 2026! Proud to have inaugurated yesterday the very first pre-workshop tutorials. Tomorrow, Olivier will join the panel “A Ghidra Moment for Hardware?”. You can also meet Texplained at the event! #HardwareSecurity 💾

🚨 @DonjonLedger has struck again discovering a MediaTek vulnerability potentially impacting millions of Android phones. Another reminder that smartphones aren’t built for security. Even when powered off, user data - including pins & seeds - can be extracted in under a minute.

Trimmed some picolibc integration bloat in LiteX :): - LiteX sim boot -> ~ 20s instead of 30s. - Build size -> 1/2. github.com/enjoy-digital/…

If you glitch one, can you glitch many? Extracting automotive firmware is a challenge. @Phil_BARR3TT explains how he bypassed the IDCODE protection in several variants of the RH850 MCU family using both voltage glitching and side-channel analysis ⚡️🚗 blog.quarkslab.com/bypassing-debu…

Testing a new RF Sweep/Scan utility (C + Dear ImGui based) for the LiteX M2 SDR, here 100 MHz to 6 GHz😜:

#openFPGALoader v1.1.0 is out! 🎇 Highlights in this release: - BPI (parallel) Flash support - SPI flash access for @latticesemi ECP3 - Improved CertusNXPro support - Build time enable/disable for cables & vendor drivers - dirtyJtag improvements - Full IDCODE support for @AMDembedded Spartan, 7-Series & Ultrascale+ - Documentation updates Thanks to all contributors/users 🍻 Full release note here: github.com/trabucayre/ope…

Given a JTAG chain, walk the chain and map out the connections between all chips on the chain for which you have BSDL files (in this case, a configuration/flash mgmt CPLD and the FPGA it configures).

Le replay du stream de ce matin sur #FPGA/#LiteX, phase 1, est disponible sur Youtube avec tous les liens importants dans la description ! youtube.com/watch?v=F-rgCX…

@FlUxIuS @schen0x Nice article. I also used the resistor trick (for bi-dir detection) a few years ago: collshade.fr/articles/renes…

Just posted some notes on @schen0x's CODE BLUE 2025 talk about fault injection by traffic mocking. TL;DR: Record debugger<->chip traffic, replay it with a Pico, glitch the security check. No protocol driver needed, works on any MCU with a debug interface. Total cost: ~$10. community.penthertz.com/t/how-to-hack-…

@emh203 Nice work! I know also this work: github.com/Werni2A/OpenOr…

catharsis this will be an MR in the V11 cycle. It will be another building block for Orcad schematic import.

Started exploring how to use @GSGlabs LUNA to build a custom USB device with @enjoy_digital LiteX. ✅ LiteX now includes an Amaranth2VConverter module: it's now easy to integrate Amaranth cores. ✅ The LUNA ACM module is now integrated and can serve as a ValentyUSB alternative. Tested on the @RadionaOrg ULX4M board.

Defining FPGA from python! This never gets old. #ULX4M #LiteX

A neat tool for PCB reverse engineering & troubleshooting: PCB Tracer! (Draw pins, power lines, components over high-res photos - plus an AI mode to auto-detect components) Also listed some open-source alternatives 👇 community.penthertz.com/t/pcb-tracer-f…

Wrote an article on exploiting a partially hardened STM32H5 by using gadgets from the ROM code: errno.fr/Overflowing_ST…

#FPGA facile : petite présentation et prise en main de #LiteX avec notre nouvel article offert de la semaine. À découvrir sans plus tarder sur notre base documentaire : connect.ed-diamond.com/hackable/hk-05….

@Baldanos Thanks! Not exactly what I want but, the Tang Mega module is cheap. I could design my own board to add a FT602 to get the USB3..

@fjullien06 Tang mega ? wiki.sipeed.com/hardware/en/ta… I have one but never tested it

Any advice for an FPGA board with a USB3 bridge, DDR and a lot of I/O pins? Something like the Opalkelly XEM7310 but without paying $600...

@enjoy_digital Can you tell us how you and Codex made this possible?

Hierarchical Verilog coming to LiteX (thanks Codex 🙌) Not merged yet… but feels close though... 50k-line monster flat files, your time is up😜

LiteX 2025.12 is out! With lots of new boards supported in LiteX-Boards (For a total of 245 🤪) and lots of new features/fixes on the framework and cores. Thanks to all the contributors! Let’s build even more exciting projects in 2026!