The Electronics Reporter | Stuart Cording

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How do you protect RISC-V processors from cyberattacks? All computing systems and their processors are at risk of cyberattacks. In Stefano Di Carlo's research group at the Politecnico di Torino, his students examine the security of the open-source RISC-V core.

Why design a custom AI chip when Nvidia has such cool products? Have you tried to buy AI chips from Nvidia? Availability is a challenge! Talking to Semidynamics may open your eyes to alternative approaches that make you independent of the big AI-chip manufacturers.

Why can't cache solve the memory wall? While cache keeps memory accesses fast, it's not unlimited. At some point, cache misses occur again and the processor is left waiting for data. For their RISC-V processor IP, Semidynamics' Gazillion Misses technology solves this problem.

How do we reduce the power consumption of AI? In Stefano Di Carlo's research team at the Politecnico di Torino, students are looking at neuromorphic computing for AI, which tries to build a system that functions similarly to the human brain.

What's the benefit of RISC-V? Customization! RISC-V is an open standard process technology - everyone can use the instruction set architecture (ISA), and space is reserved for adding your own instructions. Check out these insights from Roger Espasa at Semidynamics.

Can you launch a startup from your PhD research? Years working away in a research lab has its ups and downs, but after a few years of intensive work on a problem, you'll have your PhD. Stefano Di Carlo hopes that his students will turn their ideas into businesses.

How can you reduce memory latency in your RISC-V design to zero? Cache is the typical solution for a processor that accesses data faster than memory can deliver it. Semidynamics has developed Gazillion Misses, an IP block that works alongside their RISC-V core, to resolve this.

Designed for battery-driven devices that compromise Otii Arc hardware and Otii Pro software. This energy optimization tool is for hardware, firmware, and software developers. Now available at @MouserElec elektormagazine.com/news/otii-arc-…

Hey, MCU watchers! Well, after the debacle with the first MSPM0C1104, David Prosser agreed to send me another sample of the world's smallest MCU. But would you believe it, in my excitement I've dropped it on my duvet! Can you help me find it? 😆

@lauriewired It was the same on the C5000 if I recall correctly, and the accumulator was, I think, 40 bits.

Weird byte sizes aren’t over though. In niche areas, like digital signal processing, larger byte sizes have performance advantages. The smallest addressable byte on Texas Instrument’s C2000 architecture is 16-bits. It's rare, but sometimes non-standard bytes happen!

The 8-bit byte is largely arbitrary. In the 1950s, word lengths were all over the place. No one could decide on a standard. Computers with 60, and 36 bit words led to bytes of interesting sizes, often 6 or 9 bits. That is…until ASCII came on the scene.

Hey, MCU watchers! So impressed was I with @TXInstrumentsEU MSPM0C1104, the world's smallest microcontroller, I asked David Prosser to rush me over a sample. But in my excitement, the darned thing has dropped on my rug! Can you help me find it? 😆

@greenbiz_de I think it is more challenging. In this example, people are sharing how to hack their own cars to reprogram the engine ECU. I think, more broadly, fewer people are willing to share their hacking approach as they want the spoils for themselves, such as data to sell.

@stuartcording Interesting approach! Using AI to monitor social media for automotive cyber threats could be a game-changer for OEMs. How do you see this impacting the broader cybersecurity landscape?

Can you stop automotive cyber attacks by monitoring social media? Researchers working with Stefano Di Carlo at the Politecnico di Torino are using AI to monitor these changing threats and inform OEMs, enabling them to respond.

In our interview with Alfredo Neumann from Elatec, we discussed how they simplify the complex world of access control. Smart offices and factories rely on such systems for physical access, PC single sign-on, and fleet management. elektormagazine.com/news/unifying-…

Why can't cache solve the memory wall? While cache keeps memory accesses fast, it's not unlimited. At some point, cache misses occur again and the processor is left waiting for data. For their RISC-V processor IP, Semidynamics' Gazillion Misses technology solves this problem.

Is it possible to defeat automotive hackers by monitoring social media? Prof. Stefano Di Carlo from the Politecnico di Torino is using AI prediction models to highlight automotive firmware hacking threats as they emerge. Full video interview for HiPEAC on YouTube and LinkedIn!

📺 New video on #HiPEACTV! 👉 youtu.be/rd_pCCj6kGQ @stuartcording Stuart Cording speaks to Stefano Di Carlo about RISC-V, #automotive, #cybersecurity, #safety and #resilience in computing systems. Plus, find out why doing a PhD can open doors to a fascinating, satisfying career, whether you decide to stay in academia, join a company or start your own business venture.

How do you know you've hit the memory wall? Developers create AI algorithms that end up getting stuck waiting to grab data from memory. Yes, there is a cache available, but it only has limited use. If the data's not in the cache, time is lost waiting to get data from DRAM.

Join us in 30 minutes to learn what goes into building a Battery Storage System (BSS) with @NXP! Bring your questions and join us on LinkedIn at 16:00 CET here loom.ly/Achxbrg together with ElektronikPraxis for a tremendous deep tech discussion!