Matt Hurd

@AlexanderGerko mc

msvc has a candidate fix in Visual Studio 2019 version 16.10 Preview 2. impressively quick turnaround. developercommunity.visualstudio.com/t/parameter-pa… gcc has ack'd the codegen problem #cpp #cpp20

@scottnewham @ChrisWooldridge @mattgodbolt @Usborne Scott, the master of the MicroBee 🐝🙂. Did any MicroBees sell outside the land of Oz?

@ChrisWooldridge @sumohurd @mattgodbolt @Usborne I had a copy of the Z80 book... and just found this z80.info/zaks.html Having a re-read, what a great explanation of concepts...

Just been re-reminded of the amazing book I learned assembly from: drive.google.com/file/d/0Bxv0Ss… - freely available, thanks @Usborne ! (Though... for Z80 and 6502 :) )

@ChrisWooldridge @mattgodbolt @Usborne Love that :-)

@sumohurd @mattgodbolt @Usborne My z80 notes - circa 1982

@ChrisWooldridge @mattgodbolt @Usborne Zaks wrote a lot on the topic, but I had a hard time liking the Z80 with its nonorthogonal I/O as a wee kid. The lack of beauty horrified me :P I grew up with 6502, 68000, PDP-11 assembler before eventually relenting to the 8088 dark-side. Stuck to BASIC on CP/M machines

@sumohurd @mattgodbolt @Usborne Didn’t Rodney Zacs write the Z80 bible also?

@jfbastien @BarryRevzin @vzverovich @CppSage @shafikyaghmour 9 "cases" in ieee std_logic: cs.sfu.ca/~ggbaker/refer…

@BarryRevzin @vzverovich @CppSage @shafikyaghmour tribool

How does one detect if bool contains an invalid value (something other than 1 or 0)? Asking for a friend.

@vzverovich @Cor3ntin !!

@Cor3ntin I want to convert invalid bool into 1 or 0

@mechmarkets @TradingDutchman @ltabb @kmcpartland Most of the latency is in the serdes whether it be an ASIC or FPGA. Building a better serdes is hard...

New news on the HFT front. Building new trading logic into chip via ASIC This Startup Is Building a Chip to Save Traders Vital Microseconds bloomberg.com/news/articles/…

Three compilers, three different results. godbolt.org/z/cEoYrn4T8 Bugs filed for msvc and gcc after .@zygoloid clarification: gcc.gnu.org/bugzilla/show_… msvc gets it right without the auto param with an explicit template pack expansion. icc/edg, clang, & msvc agree #cpp20 #cpp

@__phantomderp Perhaps not reddit approved on r/cpp? Below + godbolt: godbolt.org/z/G1s5oafno

@__phantomderp Fun compiler bugs: reddit.com/r/cpp/comments…

Cursed c++. Look ma, no commas... and enough space to compile 😐 godbolt.org/z/81bPfGY97

@Mikenicholls88 German proverb: Dienst ist Dienst und Schnaps ist Schnaps

Is there a German word for a trip to Bunnings where you don't find anything you need?

@aosipovich HFTs are often approached to subsidise expensive LEO satellite services which *increase* latency 🤕

Not an April Fools joke! HFTs are exploring the use of low Earth orbit satellites for sending data over trans-continantal routes. Will space be the final frontier of the low-latency arms race? wsj.com/articles/high-…

@AlgoTrdr @experquisite @JoeSaluzzi As long as it represents a proper intention to trade, otherwise you're in dangerous territory

Interesting notice from Cboe warning their members not to submit "partial message packets for the purpose of seeking to reduce latency". cdn.cboe.com/resources/regu…

@experquisite @AlgoTrdr @JoeSaluzzi AFAIK Nomura at JPX (nee TSE) were the first I know of to do this. ~2.3us back then which is v slow by today's standards

@AlgoTrdr @sumohurd @JoeSaluzzi One thing people sometimes do/did is start streaming out an order packet and if they contemporaneously decided to abort the order they spoil the Ethernet CRC at the end. Same class of shenanigans.

@AlgoTrdr @JoeSaluzzi Mostly. Just a TCP header would likely be an ill formed pkt unless the ex supports IP fragments - some do - most don't. Sending two pkts each with a tcp header to form a complete ord message depending on the ord msg header component may help. OOO TCP - tail first - can also work

@experquisite @PaulWestmontUsa @AlgoTrdr @JoeSaluzzi Pkt invalidation used to be hidden as most ex's didn't monitor data link layer errors, but some ex's now get annoyed by this due to better logging. FIFO ts determinism lowers ord jitter => inbound latency more critical & pkt fragments create complexity & possible errs

@PaulWestmontUsa @AlgoTrdr @JoeSaluzzi Possible also the CME’s switch to iLink perfect time stamped FIFO (vs messy round-robin) exacerbated this? @sumohurd might comment