Tech Fund

Leading Edge Semi Shortages - a deep dive techinvestments.io/p/leading-edge…

Goldman - the leaders in enterprise AI coding can sustain their lead due to the data flywheel: "Compared with consumer AI data sets, enterprise AI has a unique positive flywheel of coding data (with clearly defined success/failure scenarios that can then feedback for consistent model iterations/reinforcement learning post-training). We believe this positive loop will enable Zhipu to sustain its #1 leadership position in enterprise AI coding scenario, where such leadership could even widen based on global examples. We see GLM5.2’s recent out-performance (ranked nearly on par with US SOTA models, on Arena AI based on actual user feedback) as a landmark moment for Chinese AI models’ intelligence (we call it the “Zhipu GLM-moment” as models reach the overall performance threshold for wide adoption) after the DeepSeek moment (where breakthroughs were mainly on cost efficiencies)."

@DeroostArno Xfab is mostly CMOS, smaller MEMS business

@techfund1 How does the capabilities and end markets of Silex compare to Xfab?

@fullbidlift he's the semis analyst, doesnt cover PENG

UBS - $MRVL has the leading market share in CXL products Following our latest CPU work, we believe the CXL opportunity is inflecting with players like MRVL and ALAB positioned to benefit as we move towards the end of the decade. Cache-coherent, low-latency, high-bandwidth interconnect built on PCIe is expanding the market, and CXL is becoming a critical enabling technology. We believe MRVL has the leading market share in CXL products to date but we do see ALAB and maybe AVGO becoming larger players as the market expands, with the CXL-related ASIC attach market reaching $7–10B by 2030E given applications evolving from single-CPU memory expansion toward rack-wide and multi-rack CXL fabrics connecting CPUs and XPUs. We expect CXL revenue to reach ~$1B in C2027E for MRVL, largely driven by XPU-attach within racks, with incremental support from agentic CPU demand. CXL revenues span three categories: interconnect (legacy expander use cases), XPU-attach (newer custom hyperscaler designs, where MRVL has five programs with two major US hyperscalers including for MRVL’s Google TPU (we think)), and switching (CXL switches). The company has indicated that the bulk of the ~$1B target for CXL revenues is tied to XPU- attach sockets rather than CPU-attach, and agentic tailwinds to the CPU adoption are incremental to existing XPU-focused programs.

@HelionTrading much cheaper than hiring additional engineers. small developers can't afford, but enterprise can

@techfund1 The cost is atrocious, beyond gouging. They will be forced to retreat shortly

Coding with Claude Fable is extremely addictive, expect Anthropic ARR to skyrocket Long semis

Goldman: TSMC accelerating capacity buildout We now expect N3/N2 wafer-out capacity to reach 200kwpm/140kwpm by end-2027E (vs. 190kwpm/130kwpm prior), as we see stronger demand from customers especially for AI/HPC applications. On the back-end, we also raise our 2027E CoWoS (incl. WMCM) capacity to 280kwpm (vs. 250kwpm prior). As a result, we lift our 2027E capex to US$78bn (vs. US$70bn prior).

This is years away. First, there will be a pilot line. Then, if that's a success, there will be a scaled up fab. All this stuff takes years.

If UBS is correct here, $CBRS is going to be a nice performer.. "Our conversations with experts and takeaways from recent industry events suggest compute is likely to continue moving along disaggregation route which offers significant performance improvement on the system level. Although AWS has not yet been fully formalized, we think the upside scenario would imply some deployment ratio of CBRS WSE CS- 3/4 per Trainium 3 rack (we estimate at 20K in C2026), but also potentially deployed alongside older racks too. We estimate AWS shipments potentially reaching $4-10B/yr before the end of the decade and think the opportunity may be measured in $10Bs in annual hardware shipments over the longer term. Beyond AWS, we see MSFT potentially interested in disaggregated solution over time, once MAIA 300/400 are ramped and widely deployed."

SiC Power Semis - China’s Yangjie Tech says capacity is fully booked (SCMP) Positive indicator for $IFX $WOLF $STM The SiC industry has been in strong oversupply in recent years, so as more companies can't meet rising demand, this is a bullish indicator that orders will also be coming towards $WOLF. $WOLF's New York SiC fab remains heavily underutilized, so fresh order flow will give it tremendous operating leverage.

Anthropic mentions Sonnet 5 uses 1-1.35x more tokens Theoretically good for ARR, however, Sonnet 4.5 does such a good job at the workflows I use it for that I don't see the reason to change my API calls

@DavidTimis here you go techinvestments.io/p/asmls-strate…

@techfund1 Care to elaborate?

Rising DRAM capex will drive a boom in EUV orders The reason is that Litho intensity at the next DRAM nodes will grow even faster than in TSMC's logic roadmap - $ASML

@JCJC915661 In DRAM the Chinese can't even access EUV + advanced immersion tools

@techfund1 China's CXMT and YMTC?

There's just no way out of this DRAM shortage in the coming years "Even as we expect industry supply to improve gradually in 2028, we currently do not have line of sight as to when memory supply will be able to catch up with increasing demand. Memory industry supply growth is dependent on significant greenfield fab expansions. These greenfield projects are large, complex and time-consuming. Further, the pace is constrained by several factors, including long lead times for fab construction across the world, shortage of workers with critical trade skills, complex regulations, including permitting and the need for enhanced energy infrastructure. Meanwhile, memory process technology which is among the most advanced to develop and manufacture in semiconductors is getting more complex with every new node." - $MU CEO

"early testing shows that Jalapeño will deliver performance per watt substantially better than current state-of-the-art. A detailed technical report on performance will be presented in the coming months. The architecture reduces data movement and balances compute, memory, and networking resources to achieve realized utilization much closer to theoretical peak performance. Jalapeño is a blank-slate design for modern LLM inference, not a general-purpose accelerator adapted from earlier AI workloads. It is informed by the systems OpenAI runs every day across ChatGPT, Codex, the API, and future agentic products, while also being designed for current and future LLMs across the industry. The goal is to combine the power and throughput of today’s leading AI accelerators with latency closer to the fastest specialized inference systems, making Jalapeño well suited for interactive LLM products at scale. That is the full-stack advantage. OpenAI is not only developing frontier models or building products on top of them; it is designing the infrastructure underneath them: chip architecture, kernels, memory systems, networking, scheduling, deployment systems, and product experience. Because OpenAI operates across the stack, each layer can be optimized around the same goal: making its models faster, more reliable, and more affordable for users."