Chips & SaaS

If MTK TPU succeeds, SMTC is a 2-4x from here. If MTK TPU fails, SMTC is a 1.5-2x from here. SMTC CTLE can give 4-7 dB SNR gain. ~300G SerDes at PAM6 has 4-5 dB SNR penalty from theory. MTK would need 2-4 dB improvement in design + CPC + SMTC CTLE + good EMIB pkg to make it.

Citi on $INTC / $TSM & ABF: "ABF technology readiness is critical for EMIB-T Adoption — Given EMIB-T’s design methodology, the readiness of the ABF substrate ecosystem for ultra-high-density routing, precise bridge embedding, and advanced power delivery is critical for EMIB-T adoption. We believe the capacity and technology readiness will be key checkpoint for EMIB-T penetration in the next 2-3 years."

UBS raising $MU pt to... $1,625

Doesn't look like a huge breakthrough. They're using a technique that's expected to be done by everyone - because they can't scale litho, they've accelerated other parts of the roadmap. Logic splitting is best shown in AMD's 2021 roadmap. It requires tight pitch TSVs and best in class HBI. So even if it comes out in 2026/2027, Huawei still has a way to go to hit 14A equivalents by 2031 using SMIC multipatterning. Also what is equivalent here? Chip perf? Logic density? Power? All of them? DTCO has been part of node and chip design for many years, and is often heralded as a 'node or better' uplift when done right. 2031 having 14A equivalent might be SMIC 7+++++ in reality. As in, each node has lots of improvements to make if you get stuck on it for a while.

Huawei says it has made a breakthrough and expects to design high-end chips with transistor density equivalent to 1.4 nm processes by 2031.