Zero-Day Labs

Great news from the CVA6 Hypervisor workshop in Aix-en-Provence attended by @Thales, University of Minho, @openhwgroup, PlanV and PULP! We have just merged Hypervisor Extension by Bruno Sá into the CVA6 master branch github.com/openhwgroup/cv…. Thank you for reporting @niwist.

Luca's paper @lavalucente "A Heterogeneous RISC-V based SoC for Secure Nano-UAV Navigation" is now on arXiv. Get to know Shaheen, our heterogeneous SoC in GF22, Linux-capable RV64 core, compliant with the v1.0 Hypervisor extension arxiv.org/pdf/2401.03531… @mattia_siniga @niwist

We have finally openned up our website 🚀 Visit us at 👉 osyx.tech to get to know more about our commercial services and read more about our story.  Press Release here 👇: osyx.tech/2023/07/05/int…

Join us for S4/E2 of #OpenHWTV! Members from @openhwgroup @AxeleraAI @10xEngineers and @thalesgroup will lead viewers on a journey of the #opensource #RISCV processor CVA6 from Ariane ➡️present. CEO, @FlorianWoh will end the episode with a live Q&A! 📝tinyurl.com/37t9bnuj

I'm thrilled that our work "BUSted!!! Microarchitectural Side-Channel Attacks on the MCU Bus Interconnect" was accepted at the most selective and prestigious academic computer security conference, i.e., IEEE S&P24. So proud of my team! @_CRodrigues__ @danieljcoliv Camera-ready version of the paper here 👇: bustedattack.com/resources/BUSt…

To the best of our knowledge, the first @risc_v silicon with hardware virtualization support (a.k.a Hypervisor Extension) 😎🚀 go go @lavalucente

Ready for @risc_v Summit China starting this morning. More than 2000 registered for onsite, sold out! Thousands more will watch the live stream and join local parallel events. This community is changing the future of computing! riscv-summit-china.com