Andreas Olofsson

I am done with Twitter. See you in the real world.

@ayazdanb Thank you for the kind words Amir!

@zeroasic Thank you Andreas really for transforming the hardware design ecosystem!

Finally, a proper "pip/npm for hardware", major SiliconCompiler upgrade, SiliconCompiler.com . Try it! import siliconcompiler import umi # design chip = siliconcompiler.Chip("top.v) chip.use(umi) # pulls in dependencies # your code chip.run()

Get ready for the post Moore wafer-scale era. Check out our latest paper showing RTL simulation of a million cores processor. (RISC-V) arxiv.org/abs/2407.20537

@devbisme @njrabit Working on it...

@zeroasic @njrabit Under supported devices, it says "ZA". I assume this means ZeroASIC. Will any Lattice, Xilinx, or Altera devices be supported?

We just open sourced Logik, our light weight Python based FPGA toolchain. No more TCL and 100GB binary blob downloads! Please try it,we are proud of this work.🙏 github.com/zeroasiccorp/l… $ python -m pip install --upgrade logik

This post shows how to build and verify your own chip(let) in Python. Writing SV testbenches is not fun, Switchboard and SiliconCompiler improves life quality! 😉Try it out and let us know what you think. zeroasic.com/blog/ebrick-de…

If you haven't tried SiliconCompiler yet, you really should;-) Convert Verilog to GDS in one line. $ pip install siliconcompiler $ sc <yourmodule>.v

@satnam6502 Sorry to hear that, but not surprised. The process of renewing a Swedish passport has become outright hostile...same goes for immigration (personal experiences).

Not the warmest welcome to Sweden. The immigration official wanted to see proof of my departing flight and proof of a hotel reservation, and he gave me some stiff questioning about why I am visiting. I am now starting my visit to Gothenburg feeling like a suspected criminal.

We have decided to open source "switchboard", the powerful low latency communication library at the core of our emulation platform. It may look easy, but it's not. github.com/zeroasiccorp/s… zeroasic.com/blog/switchboa…

@RajaXg End customers are definitely becoming more demanding. 2000: Give us FFT, blas libs + datasheet, we'll do the rest.. 2010: "How do I write parallel programs?". It better not be harder than serial codem 2020: How fast/efficient can you perform X? 2030: Just give me answer...

And these sand castles today are being productively built on two abstractions that have been stable for the past two decades..SMT and SPMD. And taking this analogy further, nVidia is offering the most accessible beach front for AI kids to build these wonderful castles. Other beach fronts (Apple, AMD, Intel) are starting to get accessible if you are willing to jump some walls, wade through rough terrain and scrape your knees. And co-incidentally all of these are still built on SMT/SPMD abstractions..

We have open sourced our "Universal Memory Interface" protocol for chiplets. Includes a complete reference implementation. Spread the word.🙏 github.com/zeroasiccorp/u…

Hi old friend! Zero ASIC came out of stealth today to launch the ChipMaker ASIC design and emulation platform. I can almost guarantee that you have never seen anything like it. Try it out and let me know what you think! zeroasic.com

@soronpo @antmicro @CHIPSAlliance @f4pga @XilinxInc @QuickLogic_Corp @latticesemi @siliconcompiler @OlofKindgren The @f4pga developers are all familiar with fusesoc, edalize, siliconcompiler. I am sure they have good reasons for their approach, perhaps they can comment?

@antmicro @CHIPSAlliance @f4pga @XilinxInc @QuickLogic_Corp @latticesemi I feel we are reinvesting work where there is already a noticeable effort of good solutions. Paging @zeroasic for @siliconcompiler and @OlofKindgren for edalize.

Our recent project within @CHIPSAlliance @f4pga group involves a new #Python build system & unified f4pga CLI tool, allowing us to wrap the underlying tools into a single CLI, making F4PGA a more complete toolchain: antmicro.com/blog/2022/09/f… @XilinxInc @QuickLogic_Corp @latticesemi

@soronpo @WhiteHouse yup

@zeroasic @WhiteHouse Am I seeing this correctly? Only once (and only in security context)?!

@satnam6502 Wishing you a speedy recovery! I got it at DAC in july and was down for a couple of weeks.

I tested positive for COVID-19 this morning after returning from the #ICFP2022 conference. I've avoided it so far and my six vaccinations were only going to do so much. If you were around me then I am sorry and please consider testing. Earliest possible symptoms: Friday 16 Sept.

@mtaht Wow, that's amazing, I did not know that. I will keep that in mind when we get close to an IPO.😀

@zeroasic redhat offered 500 shares at the IPO to everyone that had ever worked on #linux. I thought that was going to be the way we created a virtuous circle, but no....

Why isn't there a "Nobel prize" for open source? The companies that made trillions off open source infrastructure need to step up! I am tired of seeing my heroes spending decades working for free without proper monetary recognition. (please share). 1/n

@jcawley01 Fellowships can be very effective. Maybe @gvanrossum can comment on how his stint at IDA helped push Python forward?

@jcawley01 Yeah, the Nobel price is more of an appreciation gift, doesn't really affect outcomes. Still, long service should be rewarded.

Who did I miss? n/n

Aliaksei Chapyzhenka for wavedrom 10/n