Antmicro

We introduced a new resynthesis strategy in the @OpenROAD_EDA ASIC design toolchain, based on a genetic algorithm. See how this approach can help you optimize your design and how it complements the existing simulated annealing strategy we developed previously: antmicro.com/blog/2026/05/g… @Google

With @renodeio support for the @RISC_V @Andes_Tech D25F core, platforms like the Egis ET171 can be simulated easier. Find out how we expanded the fingerprint module test suite for @Google's @ZephyrIoT-based Chromebook EC and how Renode aids in CI-driven testing of production-grade devices: antmicro.com/blog/2026/05/a…

Our new open hardware SDI-Fiber Adapter enables reliable, high-quality video transmission over long distances in challenging, high-EMI environments. Learn more about the design and our customization and integration services: antmicro.com/blog/2026/04/s…

We're on track towards the next big milestone for Verilator: read about our proposal for initial support for four-state logic, and join us at @FossiFoundation's Latch-Up 2026 in Canada this weekend to learn more: antmicro.com/blog/2026/04/i… @CHIPSAlliance @linuxfoundation

Antmicro's open hardware baseboard for @NVIDIA Jetson Orin available to buy directly on System Designer! Max flexibility in small footprint to kickstart your next edge AI device: supports Orin Nano/NX, customizable, multiple power sources & interfaces, compatible with our OSHW video accessories. Use our services to take your project from PoC to a customized, future-proof product ready for deployment at scale: OTA with RDFM, AI benchmarking and deployment with Kenning, factory testing with Protoplaster, and more. Now also available with fast, direct shipping in Europe: designer.antmicro.com/library/device…

Read about the recent improvements to our DC-SCM reference platform and other related developments, and meet us at the @CHIPSAlliance booth at @OpenComputePrj #OCPBarcelona26 to learn more about our data center-oriented tools and workflows: antmicro.com/blog/2026/04/i… @latticesemi @NXP

Join us at @FossiFoundation Latch-Up 2026 to learn about our recent contributions to the Verilator project, including improved verification, UVM support, and the next major milestone, four-state logic support: #the-next-big-step-for-verilator-towards-four-state-logic-and-new-developments-in-uvm-compatibility" target="_blank" rel="nofollow noopener">fossi-foundation.org/latch-up/2026#… @CHIPSAlliance @linuxfoundation

In our first talk at @FossiFoundation Latch-Up 2026 we'll walk you through the activities and objectives of the recently restructured @CHIPSAlliance SV Tools Project, and discuss tools such as Verible, RISC-V DV and SV-tests: #chips-alliance-towards-a-unified-open-source-asic-design--dv-workflow" target="_blank" rel="nofollow noopener">fossi-foundation.org/latch-up/2026#… @linuxfoundation @risc_v

We expanded our open source thermal simulation flow with a Computational Fluid Dynamics-based methodology for steady-state simulation of conjugate heat transfer in complex designs. See how we tested this approach on an @NVIDIA Jetson AGX Thor setup: antmicro.com/blog/2026/04/s…

The @CHIPSAlliance @risc_v VeeR EL2 core includes an optional Dual-core Lockstep mechanism for applications such as side-channel mitigation & rad-hardening. See how DCLS can enhance your safety-critical aerospace, automotive and industrial control systems: antmicro.com/blog/2026/04/d…

Happy to be sponsoring @FossiFoundation Latch-Up 2026! Get up to speed with Verilator's latest verification capabilities, UVM, assertion support, and the next big step: 4-state logic, and learn about the new @CHIPSAlliance SV Tools Project fossi-foundation.org/latch-up/2026 @linuxfoundation

Meet us at @OpenComputePrj's OCP EMEA Summit. Bridging the breadth of @CHIPSAlliance projects, we'll showcase Guineveer, an extensible @RISC_V reference design based on VeeR EL2 and Topwrap, and the open source lint/debug/verification capabilities enabled by the new SV Tools Project chipsalliance.org/news/chips-all…

See how you can now connect @renodeio to the Internet on macOS through the recently introduced vmnet support using socket-based networking: antmicro.com/blog/2026/04/r…

Introducing STEPhen, a CLI tool for automated mechanical BOM generation based on STEP files, and recreating STEP files from separate parts. See how you can use it to ensure consistency across all files documenting your design transactions: antmicro.com/blog/2026/04/g…

#CHIPSAlliance launched the #SVTools Project to facilitate open source development of SystemVerilog and UVM codebases. The initiative groups tools like Verible and Synlig for #OpenSourceSilicon and #OpenHardware. @antmicro @google 🔗 chipsalliance.org/news/sv-tools-…

CHIPS Alliance is heading to #OCP EMEA 2026 (April 29–30). Join us at Booth B54 with @Google & @antmicro to discuss #OpenSourceSilicon and see the Guineveer RISC-V design. Sessions cover #Caliptra, OpenPRoT, and AI infrastructure. 🔗 chipsalliance.org/news/chips-all…

Antmicro is extending the capabilities of @AetheroSpace's growing fleet of next-gen space computers NxN and NxA with full-stack development around @NVIDIA Jetson Orin and Jetson Thor edge AI platforms @SpaceX #Falcon9 #Transporter16 @ZephyrIoT @NVIDIAAI antmicro.com/blog/2026/03/a…

Expedite SystemVerilog tool debugging with the improved sv-bugpoint which can now speculatively merge subsequent minimization attempts into a larger group verified in one try. Check out the Verilator examples to see how it works: antmicro.com/blog/2026/03/o… @CHIPSAlliance