SpinalHDL

SpinalHDL webinar the 16 december : datenlord.github.io/en/spinal.html

@iamtommythorn @ferristweetsnow HDL for "Hardware Description Library" of course ^.^ Library in the meaning of being a set of function/utilities in a Scala / Python / Rust and all the other rainbow's colors

.@bcantrill just saw your soul of a new server talk, and it was highly enjoyable! Lots of things resonated with what we're doing at graphcore in oslo.

@pdp7 @enjoy_digital Ahh likely the template on which that is based suggested uarch to be organisation,cpu_name

@WillFlux @fpga_dave @mad_archer_ @dolu1990 @enjoy_digital It has LRSC + AMO support in the D$ (single CPU system). But this can be disabled to save area. So that's why the emulator layer still contains the atomic emulation as a fallback. There is also the cacheless config, which only implement LRSC in hardware and need the emulation :)

@fpga_dave @mad_archer_ @dolu1990 @enjoy_digital I thought VexRiscv had atomic support now?

@jackakattack @OlofKindgren @tom_verbeure @chisel_lang Thanks :)

@SpinalHDL @OlofKindgren @tom_verbeure @chisel_lang Congrats on VexRiscv's win in the RISC-V Summit SoftCPU Contest by the way!!!

Hey twitterettes, I'm looking for a logic optimization tool that can create the most efficient expression that maps an n-bit input to a 1-bit output by specifying which input vectors that produce 1,0 or are allowed to be either. It takes time to do many of those by hand on paper

@jackakattack @OlofKindgren @tom_verbeure @chisel_lang Right, rocket-chip inspired the VexRiscv decoder implementation quite much :)

@OlofKindgren @tom_verbeure @SpinalHDL Rocket-chip (in @chisel_lang) similarly uses Quine-McCluskey to generate minimized decoder logic. Might be interesting as another example: see github.com/freechipsproje… and github.com/freechipsproje… for reference.

@dvc94ch @BruceHoult @oe1cxw @symbiotic_eda @marcschettke @bitshiftmask @ico_TC @rustembedded @rustlang @llvmorg VexRiscv RVC done released :)

@BruceHoult @oe1cxw @symbiotic_eda @marcschettke @bitshiftmask @ico_TC @rustembedded @rustlang @llvmorg picorv32 supports the C extension and vexriscv has wip support for the C extension. Are there any other popular foss riscv softcores with a large userbase that don't support the C extension? Ideally at some point we'll also support rv32i and rv32im for educational cores.

Newsletter Number Nine! internals.rust-lang.org/t/the-embedded… - RISC-V bare metal support lands in @rustlang nightly, and an RFC to use @llvmorg's LLD as the default linker for `thumb*` targets!

@Benathon @Neko_Ed *out of sync*

@Benathon @Neko_Ed I recently changed the memory mapping of Briey and Murax, Maybe you are experiencing issue because the VexRiscv hardware is out of thing from the software memory mapping ? Try to git pull everything again and regenerate things :)

@Benathon @Neko_Ed What do you mean by the stack ? the SP register ? There is the boot assembly code that should be executed before branching main : (also contain the reset vector) github.com/SpinalHDL/VexR… So a reset only initialize the PC and some CSR

@SamuelAFalvoII Good point, i will document where the inspiration came from. Then while SpinalHDL look very much like Chisel, it isn't a clone, as - It solve many of the Chisel issues - It explore many design pattern that Chisel left over - Its implementation is completley different

@wavedrom I just commited an example where an 32 bits GPIO is directly interfaced with the CSR: #L39" target="_blank" rel="nofollow noopener">github.com/SpinalHDL/VexR… Note that the CSR rw is targeting a register. if it target an combinatorial signal, the written value will only remain one cycle

@wavedrom Feature onWrite/onRead/isWriting/isReading on the CsrPlugin added. Just be carefule as the onWrite/onRead block will happen at the very end of the component elaboration ^^ Also check out the CustomCsrDemoPlugin, is is much cleaner now

@wavedrom Ahh then i need to add a bit more API to provide an update event. shouldn't be complicated.

@wavedrom Feature added, see a simple demo which add an instruction counter and a cycle counter into the CSR : #L16" target="_blank" rel="nofollow noopener">github.com/SpinalHDL/VexR…

@wavedrom Which kind of CSR access do you need ? Read/Write is enough ? Do you need to know when an access is done at a given access (event) ?

@wavedrom @wavedrom Jakob is right :) So currently there is no clean way to add custom CSR, but it is something that i should add. I will take a look this evening to see which kind of API i could add :)

@wavedrom @risc_v Now up to 1.40 DMIPS/Mhz at 198 Mhz on Artix 7 : D

New #SpinalHDL documentation : spinalhdl.github.io/SpinalDoc Help yourself : Try it for your next #FPGA #ASIC project instead of #VHDL #Verilog

@3yakuya Try spinalHDL :) It's a scala library that allow you to describe your hardware without using this rock age #VHDL !