Papon Charles

@GMahovlic Just got gigabit ethernet support, it eat 766 Mbits/s in RX with iperf3 (in debian) :D

@dolu1990 Wow, Debian is running fast!

Running Debian with a quad core VexiiRiscv softcore + Litex SoC on a Efinix FPGA at 200 Mhz : youtu.be/dR_jqS13D2c?t=… #riscv #fpga

@fontamsoc (dhrystone with no inline, coremark with many additional compilation flags) Both number in the previous post are for 32 bits RV32IMA

@fontamsoc For single issue, it is mostly between : relaxed btb/branch timings (very close to what was used in the orconf talk at 200 Mhz): - 1.45 Dhrystone/MHz 2.96 Coremark/MHz stressed btb/branch timings + late alu : - 1.74 Dhrystone/MHz 3.41 Coremark/MHz

@dolu1990 I noticed that you have a new cpu called VexiiRiscv which is in-order with performance matching NaxRiscv. Does it mean out-of-order is not a performance booster ? Do both issues handle jump/branch instructions ? Or the 2nd issue handles only ALU instructions ?

@fontamsoc Overall, to keep the Nax area "small" on FPGA, a few concession have been made : - Rescheduling the instruction stream require to wait that all the previous instructions commits.

@fontamsoc On Vexii and Nax, both issue handle jump/branch

@fontamsoc Hi, Hmm not realy for a few reasons : - Coremark doesn't test the memory system performance (where OoO is great at) - Coremark contains a big CRC loop which use random branch (Big penality for deep OoO pipelines) - ...

@ico_TC @curliph Here it is :

@dolu1990 @curliph Can you please post the Vivado report of all the used Artix7 primitives used by your NaxRiscv gateware design? (Similar to this one)

#riscv Dual core NaxRiscv running Debian on Artix 7 FPGA : photos.app.goo.gl/4ApzY6UZqEfWrx…

@yannsionneau I think the 35T should be ok for single core 32 bits version of Nax + litex SoC, so, shuold be able to run buildroot.

@yannsionneau I only tried on Xilinx 7 so far, reason is their distributed ram are pretty good as far as my understanding goes. Not sure how well it will fit on ECP5, but it should work out the directly. everything is FPGA agnostic (but use a lot of asyncronously readed ram

@yannsionneau Yes, the L2 is very visible XD The config is : 2xRV64GC 100MHz (slowest Artix 7 speed grade), 16KB I$ 16KB D$ each, 256 KB L2.

@SpinalHDL Recording and powerpoints refered in datenlord.github.io/en/spinal.html

SpinalHDL webinar the 16 december : datenlord.github.io/en/spinal.html

@SpinalHDL Starting now on us06web.zoom.us/j/81437673401?…

@enjoy_digital @BrunoLevy01 @enjoy_digital @BrunoLevy01 Tested on NaxRiscv running debian (RV64GC@100Mhz) : -O2 => RAYSTONES=307.870 <3 With -ffast-math => 390.002

Test of @BrunoLevy01 's TinyRayTracer on Arty with VexRiscv-SMP 1 Core + FPU @ 125Mhz. Had to adapt the code a bit since was the CPU was too fast for it :): seems to give 141 raystones!

@OlofKindgren @BrunoLevy01 @suarezvictor @samsoniuk @pipelinec_hdl @ultraembedded @sylefeb XD

@dolu1990 @BrunoLevy01 @suarezvictor @samsoniuk @pipelinec_hdl @ultraembedded @sylefeb OoO designs is way too complex for me, but it was pretty mind-blowing when we did ORConf at CERN and realized even their water dispensers used OoO CPUs twitter.com/yannsionneau/s…

hmmmm I was discussing with @splinedrive about threading and interleaving and, we realized that a darkriscv configured with 32 threads use only 2845LUTs in a spartan-6, which means only 88LUTs per thread... (1/2) 🔥

@minut_e @pftbest @enjoy_digital Yes, likely it is how it works on some other arch. NaxRiscv implement some custom instruction to flush.

@minut_e @pftbest @enjoy_digital One thing to know, as there is no memory coherency, can't use the litex SD controller, nor the OHCI one, as they use DMA.