Buko
143 posts





Starship’s twelfth flight test will debut the next generation Starship and Super Heavy vehicles, powered by the next evolution of the Raptor engine and launching from a newly designed pad at Starbase. The launch is targeted as early as Tuesday, May 19 → spacex.com/launches/stars…


We're thrilled to partner with @Google on something we've been building with them - Googlebook. Premium, powerful devices designed for Intelligence. We can't wait to get it into your hands this fall. Learn more at ms.spr.ly/6013vuzjt #Googlebook #NEXT #Intel

@AprendidoEs @Silicon_Fly Time to buy!

No.1 Intel $INTC


















To put this simply: 1. Intel's Marketing vs. Reality Gap Is Exposed Intel claimed 18A would offer 32nm M0 pitch, but the first actual production product uses only 36nm HP cells, with no HD cells at all. Intel's claim was that a single EUV exposure could achieve 32nm, yet it appears yields aren't even there yet at 36nm. For Intel, this is a rather disappointing start. 2. On GAA The logic GAA pitch comes in at 76nm — significantly larger than even SMIC N+3's fin pitch of 32nm. The author's key point is that GAA is actually a technology that relaxes lithography constraints, and yet Intel still can't get it right. This means the difficulty in semiconductors isn't just about EUV equipment. Process integration capabilities — etching, deposition, cleaning, etc. — are what truly matter, and this is where TSMC genuinely leads over Intel and Samsung. 3. The transition from 18A to 14A introduces BSCON, enabling backside power delivery even for SRAM. Meanwhile, Samsung's SF3 doesn't even have inner spacers — highlighting the technology maturity gap across foundries. (In some areas, Intel's technology actually leads Samsung.) Summary: - Intel Foundry's prospects for winning external customers look even bleaker. If they're still ramping yields on easy HP cells for their own products, it's hard for external customers to place their trust in Intel. - TSMC's technological moat is reaffirmed. The gap in process integration capabilities is clearly manifesting not just in node naming, but in actual production pitch and cell composition.



looks like many people was semiconductor expert don't forget boast about N3B use mature FINFET Node , after N3E SRAM and transistor gate pitch relax and reduces EUV layers , 8% less density than N3B cost , yield , complexity need compromise 18A also same x.com/jukan05/status…















