acceler8future

Breaking the "Memory Wall": Optical Interconnects Emerge in GPU–HBM Packaging As a solution to the "memory wall," one of the chronic challenges in AI semiconductors, the memory and packaging industries at home and abroad are weighing an approach that decouples the GPU and high-bandwidth memory (HBM) and packages them separately. The core idea is to move the HBM—until now mounted right next to the GPU—a certain distance away, and bridge the gap with light (optics), allowing several times more HBM to be installed than is possible today. On the 22nd, a researcher at a major domestic memory maker said, "We're currently struggling to expand HBM bandwidth and capacity, so we're discussing with customers a plan to overcome the GPU's shoreline limit through optical interconnects and mount more HBM." Shoreline refers to the length of the chip's perimeter. In today's AI computing environment, the key factor dragging down compute efficiency is the data transfer speed of memory chips. While GPU performance has grown by leaps and bounds with each generation, the speed at which memory stores and supplies data has failed to keep pace—creating a structural performance barrier, the memory wall. The arrival of HBM, with its wide data pathways, put out the immediate fire, but critics continue to point out that bandwidth and transfer speeds still fall short of handling the explosive growth in AI compute. Until now, the industry has focused on stacking HBM ever higher to increase memory capacity and bandwidth within a confined footprint. But as stack counts climbed past 12 and 16 layers toward 20 and beyond, process difficulty rose exponentially. The technology hit physical limits, including the growing difficulty of meeting fixed height specifications. Vertical stacking has reached an inflection point—so much so that the JEDEC standards body has relaxed its HBM height specifications. The bigger problem is that if stack counts can't be raised, the alternative is to add more HBM horizontally around the GPU—but that, too, is impossible. In the current 2.5D packaging structure, the GPU and HBM are mounted tightly together on a single substrate. Within this structure, the number of HBM units that can be placed is strictly limited by the finite length of the GPU chip's perimeter—its shoreline. Even when more HBM is desired, there is physically no room to place it, leaving the industry in a structural deadlock. The alternative now emerging across the semiconductor industry is to separate the GPU and HBM and package them independently. It overturns the conventional chip-design principle that components must sit close together to minimize data transfer time. Instead of keeping the two chips adjacent, the approach spaces them apart and links them with overwhelmingly fast optical signals to overcome the added physical distance. Placing the HBM slightly away from the GPU within the board frees the design from the GPU's shoreline constraint. With the spatial limitation gone, far more HBM can be spread out laterally and packed into the board—several times more than today—without having to push stack heights to extremes. This means the total memory capacity and data bandwidth of the AI accelerator system would expand dramatically, on a scale incomparable to current systems. "Discussing Placing HBM Beneath the GPU"… Form Factor Could Change The industry is now producing a range of architectural design proposals over where exactly to place the HBM within the GPU board. The same memory researcher said, "Options under discussion range from broadly utilizing the space immediately around the GPU to isolating the HBM beneath the GPU board." He added, "In the latter case—isolating it beneath the GPU board—the motherboard would have to be extended lengthwise, so we're discussing even an overall form-factor change with the GPU maker." Specifically, the HBM might surround the GPU from several centimeters away, or a separate HBM zone might be created in the center of the board. "We're keeping every possibility open as we discuss the optimal layout," he said. "Nothing has been confirmed as an official roadmap yet, but as part of preliminary research toward next-generation AI accelerators, we're in talks with our partners." The outsourced semiconductor assembly and test (OSAT) industry is also watching this trend closely. An executive at a global OSAT firm said, "Optical interconnects are a clear trajectory. The only question is timing," predicting that "rack-to-rack and server-to-server links will go optical first, and then chip-to-chip connections within the board will follow." He added, "The larger units will be connected by light first, but optical research is moving so fast that it may not be that far off." Technically, the optical-interconnect technology linking GPU and HBM shares the same underlying principle as the technology connecting server to server inside a data center. The difference is the high technical barrier of shrinking optical-conversion technology—once used for communication between large pieces of equipment—down to the microscopic scale of a single board and chipset. An executive at a domestic developer of co-packaged optics (CPO) components explained, "As HBM stack heights approach their limit, the industry is discussing spreading the memory out laterally to maximize how much can physically be mounted." He added, "The principle is the same as conventional data-center optical interconnects, but HBM optical links that have to operate within a confined board space require optical components to be miniaturized to far smaller sizes and far higher integration density—so the technical difficulty is greater."

Sumo wrestler destroyed a 5-0 pro boxer in an MMA fight last night 😳

Samsung Electronics Achieves World's First "900-Layer V-NAND"… Countdown to the 1,000-Layer Era Samsung Electronics has become the world's first to successfully implement a prototype of 900-layer-class V-NAND technology, taking another step toward the era of "1,000-layer NAND." Amid intensifying layer-count competition with rivals, the achievement is being seen as Samsung securing a decisive technological lead in a single leap. According to the semiconductor industry on the 25th, Samsung recently realized an integrated 900-layer-class V-NAND system using "Cell Multi Bonding (CMB)" technology, which joins two 450-layer cell wafers into one. NAND flash, which stores data, is a core component in AI servers, smartphones, and data center storage (SSDs). Much like stacking floors in an apartment building, the higher the layer count, the more capacity can be packed into a limited chip footprint, allowing more data to be stored while maximizing power efficiency. It is regarded as a key technology for winning dominance in the AI server and on-device AI markets, where high-capacity, high-efficiency components are essential. In the current mass-production market, SK hynix holds the highest layer count with its 321-layer 4D NAND. However, Samsung—while preparing for mass production of its 10th-generation V-NAND (V10, 400+ layers) this year—has at the same time vaulted to the 900-layer mark at the research stage, positioning itself advantageously in the next-generation NAND market. Regarding these research results, Samsung stated that "normal cell operation characteristics were verified," emphasizing that this goes beyond mere theoretical stacking to demonstrate a level of capability that actually functions. Since commercializing 3D V-NAND for the first time in the world in 2013, Samsung has continuously evolved its processes to overcome stacking limits. In the past, it used a "single-stack" method of drilling and stacking fine holes in a single pass, but as layer counts rose, it ran into physical limitations such as wafer warpage and alignment errors. In implementing the 900-layer device, Samsung resolved wafer warpage—the biggest obstacle—by adopting an advanced upper chuck design. Misalignment errors that occur during bonding were overcome with its proprietary "new overlay correction" technology. Newly introduced bitline (BL) and wordline (WL) structures also delivered meaningful gains, simultaneously reducing power consumption and chip size. Globally, China—led by Yangtze Memory (YMTC)—is chasing Korean firms at the threshold of 300-layer-class NAND mass production. With government support and the localization of equipment, it is pursuing capacity expansion and technological advancement at the same time. If YMTC succeeds in mass-producing 300-plus layers within the year, price competition could intensify and pressure Korean firms' profitability. For this reason, Samsung's 900-layer achievement is highly regarded as a strategic move to build a technological barrier over the medium-to-long term. An industry official said, "900-layer NAND technology is not simply three times 300 layers—it is a technology that changes the paradigm of the stacking process," adding, "It sends global customers the message that Samsung remains the technology leader, and it will have the effect of limiting Chinese firms' volume and price offensive."

Male bee dies after ejaculation while mating with a queen bee

I'm having a hard time finding a color the Cybercab doesn't look good in.

Photonics is nuanced and using ChatGPT/Gemini makes you miss all of it: 1. $SIVE is actually a chokepoint and partially a bottleneck. The reason it's a chokepoint is leading CPO/optical hyperscaler players go through Sivers, likely: Ayar. Celestial. Lightmatter. Lightelligence. Poet. If you take out Sivers, you literally can't make some of their products + delay their roadmap by years. As many are sole/primary source but are heading the direction on multi-source. As for the bottleneck argument: Win Semi is the bottleneck for scaling laser production. But... the nuance is when you have capacity allocated for the next few years. You become part of the bottleneck itself if players fight you for allocation of finished lasers. That's the nuance people miss with capacity allocation dynamics. It's like saying $SNDK is not part of the NAND bottleneck when Kioxia makes all of it. But when Sandisk has the ultimate control of output supply, they become the bottleneck + have all the pricing power. Sivers controls output supply of CW lasers given allocations, and as seen with $LITE earnings, CW laser is currently bottlenecked as everyone seems to be stuck producing EMLs. 2. Like how LLMs always uses em-dashes. You can tell when people use AI when they always use the same "CW is a dumb interchangeable laser" argument or compare "power" specs after conflating different architectures. That's why your "analysts" using AI will get this wrong over and over. There's CW lasers... and then there's a specific architectural design that Sivers achieves with DFB lasers. If you compare power specs with $LITE vs. Sivers, Lumentum wins in isolation. But they're completely different laser architectures. All the leading CPO players like Ayar, chose $SIVE for an architectural reason for high power, low thermal, laser arrays. $JBL 1.6T LRO also made one of the most dramatic moats cited by their fireside chat, using Sivers lasers. If you think CW lasers are interchangeable with Sumitomo/Furukawa, and others. And can be plug-and-play... i don't know what to tell you? Again: $SIVE makes architecturally unique CW lasers for leading CPO players. 3. I'm not sure how many times I need to say this: $SIVE for 2024-2025 has been going through development contracts. People using TTM revenue or former P/S metrics are using completely the wrong metrics, when there's volume ramp in 2027. It's the same with $AAOI which volume ramps in H1 2027. $AEHR which volume ramps after qualification. $LPK that volume ramps after qualification. This is just missing qualification cycles in semiconductors and how to model financials currently. As for the $LITE comparisons (which was also my long last year): $LITE literally started off selling laser dies before acquisition of Cloud Lite and other downstream optical engine components. This is where $SIVE is at today with starting off in the laser chokepoint for CPO: People are modeling laser revenue off very isolated TAM projections. Meanwhile Sivers is targeting M&A to expand revenue for TAM projections. This is not a simple component FAU + ramp valuation modeling over with a Taiwanese company. Since Laser companies like $LITE, $COHR are known to downstream expand to make their lasers more valuable, then vertically integrate (fabs, assembly) afterward. Again, Sivers worked with Ayar and these types of companies before they all became billion dollar companies. I have high conviction knowing they know what to acquire down the ELS/optical engine stack + pluggable transceiver for TAM expansion. It's just annoying when I get people who don't understand the nuances backseat commenting wrong things about my longs. I got the same thing about $AXTI is not a bottleneck! InP isn't needed! China! back at $14. Now it's $140 I got the same thing about $AAOI "is going down 50%!" back at $65. or "AOI management is shady at $30". Now it's $170 I got the "there's nothing new with $SOI" back at $45. Now it's $170. I think I'm one of the few who actually understands the nuances with photonics, since I did call out $LITE, $TSEM, Innolight, $AXTI, $AAOI, $SOI, that outperformed both photonics markets and overall markets over the past year. And now I'm long on $SIVE.