Amaan Rehman Shah

@github Long overdue, but nice

Took us a minute, but stacked PRs are now on GitHub 🥞 github.blog/changelog/2026…

Yes

A year here and I’d sign up again tomorrow

@wafer_ai great breakdown. the real shift is inference getting first-class silicon instead of hand me downs from training. lots of different routes being taken right now. fun era to be building silicon that isn't a GPU.

🚨 OpenAI is launching GPT-5.6 Sol on Cerebras at up to 750 tps. Here's How kernels work on Cerebras Chips cerebras built a chip with 900,000 cores on a single silicon wafer. CSL (Cerebras Software Language) is a Zig-inspired DSL that gives you direct control over the Wafer-Scale Engine. the SDK is publicly documented and the programming model is genuinely the most alien one we've ever looked at. in CUDA you write one thread's perspective and launch millions. in CSL, there are no threads, no warps, no shared memory, and no kernel launches. you write code for individual Processing Elements: 900,000 independent cores arranged in a 2D mesh on a single silicon wafer. each PE has its own 48 KB of private SRAM, its own program counter, and a 5-port router connecting it to its 4 neighbors. that's actually it. no DRAM. no HBM. no cache hierarchy. 48 KB is your entire world per PE, where code and data must both fit. the programming model is dataflow. data moves between PEs as 32-bit messages called wavelets, traveling along virtual channels called colors. when a wavelet arrives at a PE on a specific color, it activates a task (a chunk of code bound to that color at compile time). tasks run to completion, then hardware picks the next activated task. tasks cannot call each other. they can only be activated. so instead of "launch N threads," you think of it like: "place code on PEs, define routes, let data flow." the memory model is also very different from GPUs. on an H100 you get 80 GB of HBM shared across all SMs. on the WSE-3, memory is 48 KB per PE, and there are 900,000 of them! this gives you 44 GB total on-chip SRAM at 21 PB/s aggregate bandwidth (vs 3 TB/s on H100). every access is single-cycle. no coalescing needed. no bank conflicts. no cache misses. but also no way to access another PE's memory. all inter-PE communication is explicit wavelet routing through the fabric. take a distributed GEMV for example. you would write a layout file that physically routes wavelets across the mesh. two PEs sit side by side. the left PE computes a partial result and routes it eastward. the right PE receives those wavelets from the west and accumulates. routing is defined at compile time. both operations are asynchronous and activate a task when they finish. you're physically routing data across silicon at 1 clock cycle per hop. cerebras is an extremely technically interesting & alien beast. reports 95-210x speedups over H100 on stencil computations. 3,000 tokens/sec inference on gpt-oss-120B. $10B+ deal with OpenAI for 750 MW of inference infrastructure. very exciting times for alternative accelerators! deep dive 1/6 by @gpuemi

peak read fr

@tomwarren We really went from the cloud back to a physical disc, full circle

I had to check it wasn’t April 1st 🤯

Just getting started. 🚀

There's a lot going on in this x-ray teardown of the Magic Keyboard for the iPad Pro. (@iFixit) ifixit.com/News/41291/dan…

@JordanGuestHou1 Best guest house in Petra!!