Matthew Ballance

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Matthew Ballance

Matthew Ballance

@bitsbytesgates

Verification methodology by day. Author and open-source developer by night. All opinions my own.

Katılım Aralık 2018
377 Takip Edilen280 Takipçiler
Matthew Ballance retweetledi
Jose Renau
Jose Renau@jrenauardevol·
WOSET is next Thursday (11/03/22). Free virtual registration lots of great open source EDA talks. woset-workshop.github.io
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Matthew Ballance
Matthew Ballance@bitsbytesgates·
@wren6991 What tool are you using to generate the program? I’m familiar with riscv-dv, but it sounds like you’re using something else.
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Luke Wren @wren6991@types.pl
When the SMT solver writes a program that starts by jumping into the second halfword of a 32-bit instruction, it's time to buckle up (the second part of this jalr instruction decodes to a c.lw!)
Luke Wren @wren6991@types.pl tweet media
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Matthew Ballance retweetledi
Dennis Brophy
Dennis Brophy@dennisbrophy·
Accellera will host an online workshop to discuss the parallelization of #SystemC simulations on 7 April 2022. The workshop is free but registration is required. lnkd.in/gMbEyf4C
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Matthew Ballance
Matthew Ballance@bitsbytesgates·
@verilab @dvcon_us Excellent session packed with tons of actionable approaches to improve the verification planning and execution process!
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Verilab
Verilab@verilab·
Today is the final day of @dvcon_us. Join our consultants Jeff Vance and Jeff McNeal as they present their workshop entitled "Proven Strategies for Better Verification Planning" 2022.dvcon.org/presenter/prov… Join them for a live Q&A after the session. #semiEDA
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Matthew Ballance
Matthew Ballance@bitsbytesgates·
@davidcelis I’ve found maple syrup works well — for bourbon-based drinks at least
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Matthew Ballance
Matthew Ballance@bitsbytesgates·
@wavedrom If you’re thinking about adding transaction viewing to your VCD viewer that would be very interesting.
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WaveDrom
WaveDrom@wavedrom·
How would you like to see TLM events side-by-side with RTL waveform?
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Greg
Greg@GregDavill·
A little ugly, but workable. 0.1mm width enamel wire from @adafruit working well! adafru.it/3522 You would never really see the detail of my soldering unless you're under a microscope anyway. 🤏
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Greg
Greg@GregDavill·
Lets see if I've had too much coffee today. Going to attempt to bodge some wires to this FFC connector. 0.5mm pitch doesn't give much room for error The smart thing to do would be to use a universal FFC breakout, But I don't have any laying around, and where is the fun in that.
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Matthew Ballance retweetledi
Mohamed MK
Mohamed MK@mkkassem·
chipIgnite one - up and running in seconds. It is using Caravel with clock mesh patch to address timing issues with metal only changes.
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Matthew Ballance
Matthew Ballance@bitsbytesgates·
@SVAssertions @bdmurdock This will enable use cases such as creating a sequence-class instance in Python and passing it to SV to run on a UVM agent. Most important, it should make adding Python to a TB an incremental step. Stay tuned, I expect to begin writing about it soon (in the next month or so)!
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Matthew Ballance
Matthew Ballance@bitsbytesgates·
@SVAssertions @bdmurdock I'm currently working on (and have been for about a year) a more ambitious framework to enable simulation-centric cross-calling between languages such as SystemVerilog and Python.
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Matthew Ballance
Matthew Ballance@bitsbytesgates·
@SVAssertions @bdmurdock Much of the performance hit in my experience is due to cocotb integrating at the signal level (vs procedure level), and not due to Python itself.
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Peter Monsson
Peter Monsson@SVAssertions·
@bdmurdock A lucky verification engineer 😂 The responses on performance are not good for cocotb 😕
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